Post-silicon clock-tuning is a technique used as part of speed-debug efforts to increase the allowable clock frequency of a chip. These days, it is not uncommon for high-end microprocessors to have cores containing a few thousand clock-tuning elements (i.e., variable-delay buffers). Each such buffer can be assigned to one of several possible discrete delay values, as part of the post-silicon speed debugging process. With the proper mix of assignments, many chips that initially could not meet targeted speed requirements, can now run within specification. With thousands of tunable buffers available on chip, the possible combination of assignments to the delay values is quite large. In addition, process variation causes the same design, once fabricated into silicon, to have different critical paths across different chips. Thus a specific buffer-delay assignment that most improves clock frequency for some chips may not be optimal for all chips. In this paper, we propose a tool we call AutoRex, that produces clock-tuning assignments automatically. AutoRex operates by taking data from a volume experiment across multiple process corners and analyzes this data using satisfiability modulo theory (SMT) solvers to create a single ¿recipe¿ for delay buffer assignments such that the clock frequency of the chip is improved as much as possible over the entire sample of chips. Our results show up to a 9% improvement in frequency using AutoRex.

Speed debug is a critical part of microprocessor diagnosis and debug. During this stage, the test engineer must determine and increase the maximum speed at which the processor can run reliably. One of the difficulties of this stage is that the pass-fail boundary, in practice, is not abrupt, but rather encompasses a non-deterministic region of behavior. Accurately modeling this non-deterministic region is particularly important since it directly influences the amount of time needed for speed debug.Current chip debug efforts often rely on the use of brute force techniques to deduce the shape of the pass-fail boundary region. More specifically, speed debug (i.e., the process of finding and fixing critical paths that prevent a chip from running at a higher frequency) requires a thorough understanding of the width and shape of the pass-fail boundary region where the chip’s behavior is nondeterministic. In this paper, we propose a statistical method based on Maximum Likelihood Estimation (MLE) techniques to infer the underlying shape of the non-deterministic region. Our method was tested on pre-production Intel microprocessors and was successful in modeling the shape of the fuzz-region in substantially feweriterations compared to a brute force approach.

Accurate delay modeling beyond static models is critical to garnering better correlation with post-silicon analysis. Furthermore, post-silicon timing validation requires a pattern-dependent timing model to generate patterns. To address these issues, a timing analysis tool was proposed that integrates a data-dependent delay model into its analysis. The approach solves for the delay by using the concept of circuit unrolling and formulation of timing questions as decision problems for input into a SAT solver. The effectiveness and validity of the proposed methodology is illustrated through experiments on benchmark circuits

Successful analysis of high-speed integrated circuits requires accurate delay computation. A number of delay models have been developed; however, none can claim to be truly robust in the face of large channel-connected regions (CCRs) with input "exclusivity" constraints. A good circuit-level delay model should: 1) consider input exclusivity constraints; 2) handle a wide range of circuit structures; and 3) have a robust underlying framework that can be applied independent of the actual device model. We present a symbolic timing analysis tool that aims to address these three goals. It uses algebraic decision diagrams (ADDs) to estimate delay within a CCR as a function of its inputs while easily handling Boolean input constraints. It starts with a simple linear resistor model for transistors and from there apply various heuristics to improve the delay estimation without altering the symbolic algorithms. It analyzes delay with simple series-parallel reduction when possible and use symbolic matrix techniques to handle more complex circuit structures. The effectiveness of our approach is demonstrated on circuits from industry used in the Alpha 21264 and 21364 instead of the usual International Symposium on Circuits and Systems (ISCAS) or Microelectronics Center of North Carolina (MCNC) benchmarks. Our delay estimates are within 10% of simulation program with integrated circuits emphasis (SPICE) for over 90% of the circuits we simulated. This difference can translate into significant savings in manpower by avoiding the need to verify many unrealizable worst case conditions with other, more costly, simulation techniques

As process geometries shrink, leakage currents and charge sharing are becoming increasingly critical problems, especially in full-custom circuit designs. Excessive leakage or charge sharing may cause functional failure at some or all operating conditions. Traditional circuit-analysis techniques may be used to verify if leakage currents are within allowable limits so as not to cause functional failures; however, unless the analysis takes into account specific input constraints for the circuit, the results may be overly pessimistic. Similar limitations exist for charge sharing. In this paper, we approach this verification problem symbolically using algebraic decision diagrams (ADDs). Using ADDs allows us to efficiently analyze leakage and charge sharing within a channel-connected region (CCR) as a function of its inputs. Exclusivity constraints are easily included in the analysis, thus allowing for more accurate (and less pessimistic) results. Our approach is general and can be applied to any arbitrary circuit structure, including a mesh. The effectiveness of our approach is demonstrated on circuits from industry used in the Alpha 21264 and 21364 instead of the usual international symposium on circuits and systems or Microelectronics Center of North Carolina benchmarks. We show that such an analysis can lead to up to a 90% difference in worst-case voltage drop. This difference can translate into significant savings in manpower by avoiding the need to verify many unrealizable worst-case conditions with other, more costly, simulation techniques.

Successful timing analysis for high-speed integrated circuits requires accurate delay computation. However, full-custom circuits popular in today's CPU designs make this difficult. A good circuit-level static timing analysis tool should 1) consider both internally or externally specified input constraints; 2) handle a wide range of circuit structures; and 3) have a robust underlying framework that can be applied independent of the actual device model. In this paper, we present RESTA, a Robust and Extendable Symbolic Timing Analysis tool that aims to address these three goals. RESTA estimates the delay for all valid input assignments, while naturally handling input constraints. We start with a simple linear resistor model for transistors and from there apply various heuristics to improve the delay estimation for the circuits without altering the symbolic algorithms. Our worst-case delay estimates are within 10% of SPICE for over 90% of the circuits we simulated.

We present our experiences generating scan-based critical-path tests for the partial-scan Alpha 21364 microprocessor, including the effects of crosstalk and multiple-inputs switching on path delay. Insufficient scan penetration made this difficult [D.Bhavsar (2002)], but a new ATPG algorithm increased our coverage. Comparison with actual silicon shows interesting results; we explain them with statistical analysis, factoring the effect of statistical process variation into the effects of crosstalk and multiple-input switching on delay. Finally, we draw conclusions about how to help make future designs amenable to speed testing.

As process geometries shrink, leakage current is becoming an increasingly critical problem, especially in full-custom circuit designs. Excessive leakage may cause functional failure at some or all operating conditions. Traditional circuit analysis techniques may be used to verify if leakage currents are within allowable limits so as not to cause functional failures; however, unless the analysis takes into account specific input constraints for the circuit, the results may be overly pessimistic. We approach this noise analysis problem symbolically using algebraic decision diagrams (ADDs). Using ADDs allows us to efficiently analyze leakage within a channel-connected region (CCR) as a function of its inputs. Exclusivity constraints are easily included in the analysis, thus allowing for more accurate (and less pessimistic) results. Our approach is general and can be applied to any arbitrary circuit structure, including a mesh. The effectiveness of our approach is demonstrated on circuits from industry used in Alpha 21264 and 21364 instead of the usual ISCAS benchmarks. We show that such an analysis can lead to up to a 90% difference in worst case voltage drop. This difference can translate into significant savings in manpower by avoiding the need to verify many unrealizable worst-case conditions with other, more costly, simulation techniques.

A 1.75 MByte L2 cache has been designed and fabricated as part of the Alpha 21364 microprocessor[1] (Figure 1), in a .18m bulk CMOS process. The cache was designed to run at 1.2 GHz, and pass-1 samples confirm this. While Alpha CPUs are known primarily for high speed, the combination of package constraints and a tight schedule forced careful attention to the integrated whole of power expenditure and the interaction of CAD with design. The cache consumes only 7% of total die power.

We introduce a new method for pruning combinational paths in a static timing verifier. Our method is fast and robust, even for networks with min-max delays on reconvergent clock trees. We will show that current techniques for static timing verification are either not robust or not efficient for such networks. We will also show that these networks are becoming increasingly important with newer low-power, high-speed integrated circuits. We propose a new pruning strategy for such networks which is both correct and efficient.

A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, especially for mapping with tight and complicated constraints. In this paper, we propose a procedure which takes into account a large number of circuit structures during technology mapping. A set of circuit structures is compactly encoded in a single graph, and the procedure dynamically modifies the set during technology mapping by applying simple local transformations to the graph. State-of-the-art technology mapping algorithms are naturally extended, so that the procedure finds an optimal tree implementation over all of the circuit structures examined. We show that the procedure effectively explores the entire solution space obtained by applying algebraic decomposition exhaustively. However, the run time is proportional to the size of the graph, which is typically logarithmic in the number of circuit structures encoded. The procedure has been implemented and used for commercial design projects, We present experimental results on benchmark examples to demonstrate its effectiveness.

We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as constant and makes the cell's delay a linear function of load. Out model is based on a different, but equally fundamental linearity in the equation relating area, delay, and load: namely, we may keep a cell's delay constantly making its area a linear function of load. This allows us to technology map using a library with continuous device sizing, satisfies certain electrical noise and power constraints, and in certain cases is computationally simpler than a traditional model. We give results to support these claims. A companion paper uses the computational simplicity to explore a wide search space of algebraic factorings in a mapped network.

A problem in technology mapping is that quality of the final implementation depends significantly on the initially provided circuit structure. To resolve this problem, conventional techniques iteratively but separately apply technology independent transformations and technology mapping. In this paper, we propose a procedure which performs logic decomposition and technology mapping simultaneously. We show that the procedure effectively explores all possible algebraic decompositions. It finds an optimal tree implementation over all the circuit structures examined, while the run time is typically logarithmic in the number of decompositions.

We present an algorithm for computing minimal-area fanout networks satisfying a delay constraint. We focus on one type of fanout network structure, the fanout chain. We show that, when using libraries designed for high-speed custom CMOS chips, the fanout chain typically produces minimal-area fanout networks for a given delay constraint. We then present fast, near-optimal algorithms to compute these fanout structures.

Static timing verification on a large full-custom design isan extremely challenging problem for which no complete solution exists.In this paper, we present our experience on the timing verification of our next generation CMOS CPU design using an internally developed tool, NTV.The entire chip, which consists of 1.2M transistors and 500K nodes, has been verified by NTV in less than 7 CPU hours on a VAX-8800.42K timing constraints were verified and 350K signal paths were traced.Among the reported critical paths, 85% were already known to designers and the remaining 15'%0were unforeseen critical paths.

Static timing verifiers need to know at which points data are synchronized with clocks in a circuit. Typically, this happens at latches and in clock qualification gates. However, in a general, full-custom VLSI methodology, the 'latch-equivalents' are far more varied and difficult to detect reliably. The authors define these synchronization points, and present provably robust algorithms to locate them in a very general class of MOS networks, including arbitrary pass gates. The algorithms have been applied to a variety of full-custom CPUs of up to 500 K devices, and have been found to work extremely reliably and quite fast.>

The authors present RACE2, a tool to find latch race-through in two-phase, non-underlapped-clock systems. Though these systems can run at very high clock speeds, susceptibility to race-through has made them difficult to design. RACE2, by detecting all race-through violations, greatly reduces the design risk on these very fast systems. It combines the exhaustive search of a pattern-independent tool with a knowledge base of fundamental principles about when races are-and are not-important. Planned enhancements include detection of saved-state races, detection of charge-share races, improved robustness, and better pruning methods for faster worst-case runtimes. For pieces of a large two-phase full-custom chip, CPU execution times are in minutes, seconds on a VAX-8800. To date, RACE2 has found five races in the chip, all of which were undetected by design reviews and logic simulation.>

A novel set of algorithms are presented to deduce timing constraints from a set of transistors. The algorithms are robust, extremely fast, and work well on a very wide variety of full-custom design styles. Furthermore, they include glitch-based timing checks: a novel class of constraints which, though vital for correct circuit function, has not been extensively treated in the CAD literature. These algorithms have been incorporated into a full-custom timing verifier, NTV.>