Both configurable computing paradigms as well as re-configurable computing paradigms have gained significant impact within the last few years. Both paradigms have shown to be effective when power consumption is a major design constraint even though the philosophies behind are quite different: configurable approaches aim to adapt an embedded processor to an application through, for example, an extensible instruction set plus other parameters that are determined during design time. They come in two basic flavors: a) starting with a fixed core that is extended by the system designer or,b) designing the instruction set from scratch for a specific application..Re-configurable approaches on the other side gain most of their benefits through run-time re-configuration. A high degree of parallelism is needed to overcome the physical deficiencies of re-configurable fabrics (e.g. FPGAs), though.The panel will discuss advantages and disadvantages of these paradigms with respect to low power.

Moore's law delivers higher performance and lower cost for FPGAs and ASICs alike, but at the 90nm process node and below, design schedules using the traditional cell-based ASIC design methodology hit a wall of uncertainty. At 90nm and below an emerging alternative ASIC design platform is either Platform ASIC or FPGAs. Which way will the cell-based ASIC designer turn for their next design?Over time, FPGAs and structured/platform ASICs are together poised to replace today's cell-based ASIC market, but which is the real answer to future digital design? Can companies really use these platforms to achieve the system cost reduction and functionality that they need to stay competitive? Which applications will migrate to these platforms the fastest? Is it possible to just tweak the existing cell-based methodology to more efficiently reach the benefits of 90nm process nodes and below? This lively panel will discuss whether it is FPGAs, structured/platform ASICs, or something else that stand to gain the most ground from the projected $25B ASIC market, and why.

This paper focuses on a particular SOC design technology and methodology, here called the advanced or processor-centric SOC design method, which reduces the risk of SOC design and increases ROI by using configurable processors to implement on-chip functions while increasing the SOC's flexibility through software programmability. The essential enabler for this design methodology is automatic processor generation-the rapid and easy creation of new microprocessor architectures, complete with efficient hardware designs and comprehensive software tools. The high speed of the generation process and the great flexibility of the generated architectures underpin a fundamental shift of the role of processors in system architecture.