Pipeline of processors allow the execution of a sequential streaming program on multiple processors. However, partitioning sequential code for Multiprocessor Systems-on-Chips (MPSoCs), and then creating the MPSoC platform for the sequential code to execute, is a challenging problem. Parallelizing/pipelining statements within a control loop will improve the throughput of each iteration and the overall performance. Existing techniques, such as OpenMP, for parallelizing control loops is agnostic of the underlying MPSoC architecture, thus limiting the possibilities for further parallelisation. Previous techniques related to distribution of statements to MPSoCs considered homo geneous processors and not automated. In this paper, we propose a novel automated parallelization/ pipelining approach to synthesize a heterogeneous distributed pipelined MPSoC to improve the throughput of a loop (critical for streaming applications). An Integer Linear Programming (ILP)-based formulation to map statements to processor configurations is presented, in order to find the most suitable heterogeneous processor configurations for maximal throughput. Our approach complements state-of-the-art parallelization techniques, such as OpenMP, to further improve the performance of an application. A complete MPSoC platform, for the Tensilica framework, is automatically generated within minutes using our approach for the tested applications.

A pipeline of processors can increase the throughput of streaming applications significantly. Communication between processors in such a system can occur via FIFOs, shared memory or both. The use of a cache for the shared memory can improve performance. To see the effect of differing cache configurations (size, line size and associativity) on performance, typical full system simulations for each differing cache configuration must be performed. Rapid estimation of performance is difficult due to the cache being accessed by many processors. In this paper, for the first time, we show a method to estimate the performance of a pipelined processor system in the presence of differing sizes of caches which connect to the main memory. By performing just a few full simulations for a few cache configurations, and by using these simulations to estimate the hits and misses for other configurations, and then by carefully annotating the times of traces by the estimated hits and misses, we are able to estimate the throughput of a pipelined system to within 90% of its actual value. The estimation time takes less than 10% of full simulation time. The estimated values have a fidelity of 0.97 on average (1 being perfectly correlated) with the actual values.

The Multiprocessor System-on-Chip (MPSoC) paradigm as a viable implementation platform for parallel processing has expanded to encompass embedded devices. The ability to execute code in parallel gives MPSoCs the potential to achieve high performance with low power consumption. In order for sequential legacy code to take advantage of the MPSoC design paradigm, it must first be partitioned into data flow graphs (such as Kahn Process Networks — KPNs) to ensure the data elements can be correctly passed between the separate processing elements that operate on them. Existing techniques are inadequate for use in complex legacy code. This paper proposes SDG2KPN, a System Dependency Graph to KPN conversion methodology targeting the conversion of legacy code. By creating KPNs at the granularity of the function-/procedure-level, SDG2KPN is the first of its kind to support shared and global variables as well as many more program patterns/application types. We also provide a design flow which allows the creation of MPSoC systems utilizing the produced KPNs. We demonstrate the applicability of our approach by retargeting several sequential applications to the Tensilica MPSoC framework. Our system parallelized AES, an application of 950 lines, in 4.8 seconds, while H.264, of 57896 lines, took 164.9 seconds to parallelize.

In this paper, we focus on systematic and efficient computation (accurate value or an estimate) of metrics such as performance, power, energy, etc. of a component-based parameterized system-on-chip (SoC). Traditionally, given models of SoC components (such as cycle-accurate simulator of a processor, trace-based simulator of a cache/memory), a designer manually determines an execution schedule of these models (such as execute processor simulator, followed by cache/memory simulator) to combine/propagate their individual results for computation of a SoC metric.

This paper presents a FPGA-based three-dimensional(3D) engine for a real-time and high-speed 3D measurement. Total amount of operations required for 3D position calculation increases according to both 3D frame resolution and 3D frame rate. We have designed a hardware-oriented 3D engine to achieve the both of the real-time and high-speed 3D range finding. We employ a linear camera model based light-section method. The engine consists of a system controller, a bus controller, a 3D computation unit and a graphic controller. The FPGA computes one 3D position in 15 clock latency with total 1.24 GOPS to achieve a real-time 3D acquisition. And we show a high-speed stand-alone 3D measurement system with the engine. We demonstrated the maximum performance of 12.5 k-frames/sec and range finding rate of 29.8 range maps/sec.

This paper presents a real-time measurement system based on the light-section method using smart image sensors. The presented system consists of multiple range finders using the smart image sensors and beam projectors. Target models are captured by the range finders from multiple directions. We carry out calibration of the range finders and show accuracy of the captured models according to the corresponding points of the calibration. We show the maximum and average range errors of 5.18 mm and 1.22 mm, respectively, at a distance of 1200 mm. We demonstrate 3-D capture rate of 10.6 range maps/s with two range finders and 6.1 range maps/s with three range finders.