Success of simulation-based functional verification depends on the quality and diversity of the verification tests that are simulated. The objective of test generation methods is to generate tests that exercise as much different functionality of the hardware designs as possible. In this paper, we propose a novel methodology that generates a model of the verification tests in a given test set using unsupervised support vector analysis. One potential application is to use this model to select tests that are likely to exercise functionality that has not been tested so far. Since this selection can be done before simulation, it can be used to filter redundant tests and reduce required simulation cycles. Our methodology can be combined with a test generation method like constrained-random test generation to increase its effectiveness without making fundamental changes to the verification flow. Experimental results based on application of the proposed methodology to the OpenSparc T1 processor are reported to demonstrate the practicality of our approach.

Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverage metrics are essential to guide the development of effective test suites. Traditional coverage metrics are defined based on either a functional model or a structural model of the design. If our goal is to select a subset of tests from a set of tests, using these coverage metrics require simulation of the entire set before the effectiveness of tests can be compared. In this paper, we propose a novel methodology that estimates the input space covered by a set of tests. We use unsupervised support vector analysis to learn such a space, resulting in a subset of tests that represent the original set of tests. A direct application of this methodology is to select tests before simulation in order to reduce simulation cycles. Consequently, simulation effectiveness can be improved. Experimental results based on application of the proposed methodology to the OpenSparc T1 processor are reported to demonstrate the practicality of our approach.

Functional test-bench development is a tedious and time-consuming process that requires tremendous engineering effort. Developing proper test-benches is crucial for both functional verification and post-silicon performance validation. Constrained random test generation is a popular approach to alleviate the burden of test-bench development. This paper presents an automatic constraint extraction tool that can be easily integrated with an existing commercial constrained random test generation framework. This tool extracts constraints by analyzing test-bench simulation data. These constraints, when added into a test-bench, can provide controllability of signals that are deeply embedded in a complex design. We develop simulation data mining algorithms for constraint extraction and demonstrate the effectiveness of our approach based on OpenSparc Tl microprocessor.

In simulation-based functional verification, composing and debugging testbenches can be tedious and time-consuming. A simulation data-mining approach, called TTPG (C. Wen, L-C Wang et al., 2005), was proposed as an alternative for functional test pattern generation. However, the core of simulation data-mining approach is Boolean learning, which tries to extract the simplified view of the design functionality according to the given bit-level simulation data. In this work1, an efficient data-mining engine is presented based on decision-diagram(DD)-based learning approaches. We compare the DD-based learning approaches to other known methods, such as the Nearest Neighbor method and support vector machine. We demonstrate that the proposed Boolean data miner is efficient for practical use. Finally, that the TTPG methodology incorporated with the Boolean data miner can achieve a high fault coverage (95.36%) on the OpenRISC 1200 microprocessor concludes the effectiveness of the proposed approach.