A methodology to create and develop electrical compact models for memristive devices is presented. It comprises a six-step algorithm that uses experimental data of memristive devices in order to obtain a compact model suitable for circuit-level simulations. The model methodology makes use of the definition of the intrinsic variables of memristive systems, to obtain the state map that describes the system, from which the mathematical expressions of the model are obtained. In order to illustrate the usage of the algorithm, a compact memristive model is developed by using experimental data from a TiO2-based resistive switching (RS) device. The resulting mathematical model is compared to the experimental data by computing the mean absolute percentage error (MAPE) between both, which results in 11%, and reduces to 6% after a piecewise approach. The circuit-level representation is implemented using a SPICE macromodel and a Verilog-A module, from which the memristive behavior is also properly reproduced.

In this paper, we propose a new scheme to find a free-collision path for complex environment maps. This scheme considers the obstacles in the configuration space as prohibited circular areas. Once the obstacles are modelled, the Non-Linear Algebraic Equation System (NAES) is formulated. Next, we apply a Homotopy Path Planning Method (HPPM) to find a set of points that conforms the solution path on the free-space. HPPM uses the Homotopy Continuation Method (HCM) and the Spherical Algorithm (SA) to obtain the solutions of the NAES emanating from the map. In the present work, we propose a scheme for partitioning complex maps into a set of local maps. This is useful for reducing the computation time. Several simulations of complex environment maps with thousands of obstacles are presented. Furthermore, a strategy to obtain the shortest path is applied. Finally, a simulation of the path tracking on Robot Operating System (ROS) for a differential mobile robot is shown.

The path planning method is an important element in the architecture of all mobile robots with certain degree of autonomy. An appropriate path planning method provides the robot the ability to move in a previously known environment while avoiding collisions with obstacles along the way. Additionally, this method should generate optimal trajectories from one point to another. In this work the optimal path is defined as the shortest one. Path planning is not an easy task, some algorithms and methods have been developed for solving this problem, however, its success is not guaranteed. On the other hand, Homotopy Path Planning Method (HPPM) is a new tool used to find collision-free paths, this takes the properties of the Homotopy Continuation Methods (HCM) to find a successful path. However, the path found by this method is not the optimal. In this work, a path planning method for a terrestrial mobile robot based on HPPM and Spherical Algorithm (SA) is presented. Furthermore, a new strategy able to obtain the optimal path is proposed. Finally, simulation results for several environment maps with hundreds of circular obstacles are shown.

In this paper, two adaptive Transimpedance Amplifiers (TIAs) for optical communication receivers are presented and compared. Both TIAs are realized in a low-cost digital 0.35μm CMOS process and fed from a single 1.8V voltage supply. A transimpedance variation range of more than 12dBΩ is attained with an almost constant bandwidth of about 1GHz. The proposed configurations are characterized by their low-power operation and low input-referred spectral noise.

A 1.5-V square-root domain (SRD) first-order filter possessing multiple operating points is presented. The basic building blocks of the filter are based on MOS translinear loops and dynamic level shifter techniques, allowing low voltage operation and an extended dynamic range. However the dynamic level shifters introduce positive feedback inducing three operating points to the filter through a negative differential resistance. A detailed analysis of such performance employing a bi-port analysis is offered. Simulation and measurement results are provided in order to demonstrate the analysis and circuits proposed.

This paper presents a mathematical procedure to obtain decomposed piecewise-linear (PWL) models. The models have been denoted as decomposed because they include the independent and dependent variables separately in a same formulation. The mathematical procedure has been denoted as hyperplanes unbending. It has been applied into the explicit model of Chua and the implicit model of Bokhoven resulting a recasting of these models into decomposed forms which can be applied to achieve the representation of univalued and multivalued PWL characteristics. The hyperplanes unbending technique is specifically useful in the task of finding a model description for PWL characteristics which are doubly-multivalued because it implies decomposing the original function, that describes the doubly-multivalued PWL characteristic, in two univalued functions related by a mapping variable.

This paper presents a method for finding all the regions where a DC solution exists in piecewise-linear (PWL) networks. The PWL network contains elements such as: conductance (or resistances), independent sources, controlled sources and nonlinear elements described by PWL characteristics. The method is general because it does not depend of any specific PWL model description. In fact, it considers the PWL characteristics defined as a set of graphic coordinates. The correct operation of the method is demonstrated by an illustrative example

This paper presents a topological method for identifying multiple static translinear loops using a graphical representation. It is found that the translinear principle has a new formulation based on graph theory concepts and it is applied to circuits containing BJTs and MOS transistors. In addition, it introduces the concept of translinear circuit for representing a translinear loop. The types of interaction between translinear loops are studied and its properties are established. The method is illustrated with a generic example.

This paper presents a new method that answers two important issues concerning a class of BJT circuits: firstly, the determination of the upper bound on the number of DC operating points, and secondly, the stability that corresponds to each of them. The method resorts to the topology of the circuit in order to achieve a systematic partitioning procedure which allows us to identify which transistor structure embedded in the circuit contributes multistable states. As result of this, the maximum number of DC operating points is established and the stability of each DC point can be assessed. Furthermore, the method can be easily incorporated in a simulation package.

A new method to determine the uniqueness of the DC solutions of a general class of transistor circuits is presented. It makes use of the topology of the circuit in order to achieve a systematical partitioning process which permits to identify which part of the circuit represents the cause of the nonuniqueness. As result of this partitioning process, a considerable reduction in the number of calculations has been achieved.>