An on-chip high-frequency sinusoidal signal generator with a calibration circuit based on a coarse-fine delay cell is presented in this work. The proposed signal generator is based on harmonic cancellation by adding scaled and time-shifted versions of a periodic signal. However, as we increase the target frequency of the generated signal, harmonic cancellation can be severely degraded by timing issues, degrading in turn the spectral purity of the generated signal. This paper proposes an architecture of a harmonic cancellation-based sinusoidal signal generator including a calibration circuit. The calibration circuit is based on a coarse-fine delay cell that can correct timing inaccuracies. Postlayout simulations of the proposed generator in FD-SOI 28 nm technology show a THD better than −60 dB in the frequency range from 173 MHz to 2 GHz.

Harmonic cancellation techniques have been exploited for the on-chip generation of high-linearity sinusoidal test stimuli. The sinusoidal signal is generated by combining time-shifted and scaled versions of a periodical signal, in such a way that by properly choosing the time-shifts and weights, the lower order harmonics are canceled. However, process variations and mismatch can degrade the effectiveness of the harmonic cancellation, since precise time-shifts and scale ratios are required. In this regard, timing inaccuracies are especially harmful in the implementation of high-speed harmonic cancelling generators. In this paper, we propose an on-chip calibration architecture that can correct the phase-shift and duty-cycle of the signals with the help of a negative feedback loop. Electrical simulation results at transistor level show the feasibility of the calibration technique for a sinusoidal signal generator implemented in ST 28 nm FD-SOI technology. Obtained results show a Total Harmonic Distortion (THD) better than -60 dB after calibration in an output frequency range from 200 MHz to 4 GHz.

Hardware accelerators have gained immense popularity in recent times for a varied range of healthcare applications. With the growth of edge computing, a large number of sensors can be integrated to enable lightweight computing for processing information. Over the years, there has been significant improvement in deep learning algorithms that offer exciting opportunities for their deployment even in safety-critical biomedical and healthcare applications. A detailed review and discussion on multiple challenges in the design of hardware acceleration catering to healthcare applications are presented in this paper. A wide range of generalized novel architectures and devices offers certain distinct advantages over the conventional processing units. Despite this development, the power and resource constraints of these platforms create significant hindrances in the acceleration of these high-risk medical applications. An elaborate analysis of the range of solutions to overcome these obstacles as well as a perspective on the need to address reliability and security concerns are presented. An alternative correct-by-construction accelerator design methodology is also proposed.

This paper discusses a discrete optimization problem of optimal design of Power Delivery Networks (PDN) in VLSI systems. In this paper, a practical case study is presented, where, in order to design an efficient PDN, the cumulative impedance of the PDN is optimized below the target impedance. For this purpose, the decoupling capacitors (from commercially available capacitors) are chosen in such a way that the minimum number of the capacitors are used, and also their optimal locations are identified. The different variants of inertia weight strategies incorporated into particle swarm optimization algorithms are used for this purpose. A comparative analysis of the performance of these algorithms is also presented.

This paper presents the timing error and power supply induced jitter (PSIJ) analyses of an inverter based high-speed comparator, including the design of common-mode body biasing feedback circuitry. Both the main circuit and the supporting circuitry have been designed and implemented in a standard 28 nm CMOS technology with power supply of 0.9 V. The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method. The mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).

This paper presents an assessment of jitter induced by power and ground (P/G) voltage variations. The assessment is based on an extended input/output buffer information specification (IBIS)-like model for capturing the effect of P/G signal variations under simultaneous switching output buffers. The implemented large signal equivalent-circuit model is validated under different test conditions having different P/G voltage variations for predicting the output signal distortions. The associated jitter analysis by predicting the eye diagram under the noise conditions is performed. The maximum prediction error for the peak to peak values of eye jitter and eye height are 7.06% and 2.59%, respectively.

An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented. Semianalytical expressions relating the PDN noise and TIE are developed based on midpoint delays of the rising and falling edges of the differential signal. The validating examples with CM driver circuits designed in various technologies comparing both the proposed and conventional approaches demonstrate a significant speedup using the proposed approach.

The HDMI open drain transmitter is designed to harvest power from the receiver, through the termination impedances during signaling. There is no local power supply needed at the transmitter side, neither any power is taken from the receiver apart from whatever power comes out of it during standard signaling. The zero power HDMI Transmitter capable of datarate 4.95Gbps, i.e. 1.65Gbps per Channel is designed in 65nm technology.

Power Integrity is maintained in a high speed system by designing an efficient decoupling network. This paper provides a generic formulation for decoupling capacitor selection and placement problem which is solved by mixed-integer programming. A real-world example is presented for the same. The minimum number of capacitors that could achieve the target impedance over the desired frequency range are found along with their optimal locations. In order to solve an industrial problem, the s-parameters data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM.

Swarm intelligence is applied to a module of high speed system design problem. To maintain power integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances' peaks is presented. The optimal values and the optimal positions of the decoupling capacitors are found using three different swarm intelligence methods - particle swarm optimization, cuckoo search method and firefly algorithm. Optimum values and locations of decoupling capacitors are obtained, by which anti-resonances' peaks of loaded board are minimized.

Integrated System Level Simulations of high speed serial links are necessary for the channel reliability and robustness. Increasing data rates and sharp transition time require high bandwidth systems. System level simulation are required to optimize channel design keeping cost of implementation at moderate or low level while meeting system level channel bit error rate requirement for high bandwidth systems. The parameters which influence the channel and it's interconnect environment are primarily governed by signal integrity and power integrity requirements. In this paper, system level robustness analysis of high speed serial links is demonstrated with external environment considerations taken into account. A strong correlation between measured and simulated results is shown. A generic methodology for high speed serial links is presented with complete analysis of package, board, termination, signal quality inrush Droop/Drop (SQiDD), decoupling network etc.