5G and beyond networks can facilitate the digital transformation of manufacturing and support more flexible and reconfigurable factories with ubiquitous mobile connectivity. This requires integrating 5G networks with industrial networks that increasingly rely on TSN (Time Sensitive Networking) to support deterministic communications with bounded latencies. Deterministic communications are critical for many industrial applications, but 5G does not natively support deterministic communications. To address this limitation, this study proposes the coordination of the 5G and TSN schedulers and presents a novel 5G configured grant scheduling scheme to support TSN traffic. The scheme uses information about the characteristics of the TSN traffic (packet size, periodicity, and arrival time) to coordinate its scheduling decisions with the TSN scheduler. The study demonstrates that the proposed scheme outperforms the state-of-the-art in the capacity to support multiple TSN traffic flows with different periodicities.

Time Sensitive Networking (TSN) is becoming the standard Ethernet-based technology for converged networks of Industry 4.0 due to its capacity to support deterministic latency requirements. However, it cannot provide the required flexibility to support mobile industrial applications required for the factories of the future. This could be enabled through the integration of wireless technologies in factories, and in particular of 5G and Beyond networks since they have been designed to support ultra-reliable and low-latency communications. This has triggered significant interest to integrate 5G and TSN networks, and first frameworks for such integration have been defined. However, the work is at early stages and the solutions to effectively integrate the two networks so that 5G can support TSN QoS levels are yet to be designed. This paper discusses current research and standardization work on 5G-TSN integration, and quantifies for a closed loop control application the 5GS bridge delay. The paper uses an example based on 5G-ACIA [1] to discuss open technical and research challenges to effectively integrate 5G and TSN.

The transition from conventional federated architectures to integrated architectures enables the integration of functionalities with different criticality with respect to safety, security and real-time on a single embedded computing platform. Mixed-criticality networks provide safe and predictable communication for functionalities with different criticality, offering benefits regarding spatial and temporal segregation. However, they imply certification challenges due to the increasing demand for features with different criticality, which lead to a significant and potentially unacceptable increase of engineering and certification costs. On the other hand, the traditional certification process relies on the assessment of the entire system where if a requirement changes, the whole system shall be re-attested. This paper analyses modularity from a system-of-system and a product line development perspective and contributes a reusable generic modular safety concept where the safety arguments that a mixed-criticality network must provide to be compliant with the IEC 61508 safety standard are defined. This safety case is used for defining the linking analyses where the way in which two industrial networks fulfil the safety-related arguments stated in the safety concept are analysed.

In this paper we present the model-based development (MBD) of a real-time simulator of a CANopen absolute encoder for the functional verification of real-time elevator controllers. Our contribution is a case-study on the present capabilities and limitations of two commercial MBD environments to support the development of real-time test components and their deployment into reconfigurable computing platforms. We discuss the rationale for the model design, the selection of development tools, the validation of the model and its real-time implementation, and how we considered the computing platform constraints when modeling the system. We describe the step-by-step synthesis and deployment of the encoder simulator in the FPGA of a commercial-of-the-shelf NI cRIO real-time controller. We also discuss specific integration and portability issues that arose when migrating the simulator to a variant of the hardware platform. From this experience we conclude that it is possible to successfully use a single model to program diverse HiL devices, provided that both the limits of the model-to-code translators and the IP integration capabilities in the MDB environments were examined beforehand. Finally we put forward an outlook about forthcoming model-based developments of the test system.

Despite the clear potential of FPGAs to push the current power wall beyond what is possible with general-purpose processors, as well as to meet ever more exigent reliability requirements, the lack of standard tools and interfaces to develop reconfigurable applications limits FPGAs' user base and makes their programming not productive. R3TOS is our contribution to tackle this problem. It provides systematic OS support for FPGAs, allowing the exploitation of some of the most advanced capabilities of FPGA technology by inexperienced users. What makes R3TOS special is its nonconventional way of exploiting on-chip resources: These are used indistinguishably for carrying out either computation or communication tasks at different times. Indeed, R3TOS does not rely on any static infrastructure apart from its own core circuitry, which is constrained to a specific region within the FPGA where it is implemented. Thus, the rest of the device is kept free of obstacles, with the spare resources ready to be used as and whenever needed. At runtime, the hardware tasks are scheduled and allocated with the dual objective of improving computation density and circumventing damaged resources on the FPGA.

This paper presents the details of a novel technique which allows for the implementation and execution of completely relocatable hardware tasks onto dynamically reconfigurable FPGAs. Our novel technique harnesses the internal configuration access port (ICAP) for inter-task communication and synchronization, leading to very little logic overheads. The advantages of this technique include fault-tolerance, as tasks could be relocated freely on the fabric to circumvent damaged resources, and high performance, due to better exploitation of the logic fabric. The work is part of a larger effort in our group which aims to build a fully operational dynamically reconfigurable computer which would satisfy the often conflicting requirements of high performance, fault-tolerance and high level programming.

This paper describes a novel scheduling algorithm for the execution of hardware tasks with real-time constraints onto partially and dynamically reconfigurable FPGAs. The Area-Time response Balancing scheduling algorithm (ATB) is inspired by the well-known Earliest Deadline First (EDF) algorithm, which is extended with a technique for reducing the fragmentation on FPGA's reconfigurable area. This technique promotes the reuse of the resources that are released when great area tasks finish their execution by smaller area tasks as long as the real-time constraints permit to do so. Providing an exclusively time-based algorithm, such as EDF, with support for dealing with area-related issues ensures the best results. Simulation results reported in this paper show that ATB misses 23% less deadlines than EDF. Moreover, since FPGA's damaged resources provoke unpredictable fragmentation on the device, ATB is currently the best scheduling option to be used in a Reliable Reconfigurable Real-Time Operating System (R3TOS).

This paper presents a new single event upset (SEU), multiple bit upset (MBU) and single hardware error (SHE) mitigation strategy to be used in Virtex-4 FPGAs. This strategy aims to increase not only the effectiveness of traditional triple module redundancy (TMR), but also the overall system availability. Frame readback with ECC detection and frame scrubbing are combined in a dynamically reconfigurable TMR architecture, designed under both spatial and implementation diversification premises. Moreover, since the strategy works on the device's bitstream domain, the basis for Virtex-4 FPGAs bitstream definition are also shown.

There are numerous mechanisms to guarantee the quality of service (QoS) of a wireless transmission. In many cases, the application layer sends hard-QoS requirements to the lower layers without negotiation. These requirements, which are defined by specific numeric values, are usually not fulfilled because of mobility or the delay between the signalling and data send procedures. Therefore, in wireless ad hoc networks, it is necessary to define a new conceptual model that changes the traditional vision of QoS integration. A new architecture is proposed; it is based on integration of the cross-layer concept and priority queueing. In this architecture, one node is aware of the state of other components of the network. The information shared between nodes includes the medium access control (MAC) layer metrics (MLM) and the network layer metrics (NLM). The NLMs contain the network topology, path gains and transmission power, while the MLMs contain the MAC layer buffer state. The case examined is a mobile wireless ad hoc network utilising smart antennas and spatial reuse TDMA. With this methodology, scheduling is improved and different QoS services are offered by using the information obtained by the cross-layer structure. Simulation results are presented for an STDMA network, with and without the new structure, and its feasibility is analysed.