This article introduces an innovative design of a low-pass (LP) negative group delay (NGD) integrated circuit (IC) in the 180-nm CMOS technology. The LP-NGD circuit is an inductorless topology constituted by RC-network with CMOS metal-insulator-metal (MIM) capacitor and polygate resistor. The design methodology is illustrated by considering the chip layout process. Then, the first run simulation is performed with the design rule check (DRC) and 2.5 mm${\times }$2.2 mm layout versus schematic (LVS) approaches. The feasibility of the CMOS LP-NGD IC circuit implementation is validated with chip-onboard (CoB). The proof of concept (PoC) of the LP-NGD miniaturized circuit was tested in both S-parameter and time domain (TD). As expected, the calculated, simulated, and experimented results of CoB showing NGD of about −10 ns over 12 MHz and −10 dB attenuation are confirmed. The active CMOS LP-NGD technology compensates the insertion loss to 2.4 dB, the GD reaches −11 ns, and the reflection loss reaches −20 dB. Moreover, TD investigations were also performed to show the feasibility of generating pulse and arbitrary waveform signal time advance through the designed and fabricated LP-NGD CoB prototypes.

This brief presents a reconfigurable inductor-less voltage controlled oscillator (VCO) with low-power and low-cost performances making it suitable for IoT applications and applicable to the multi-standards. It uses an active inductor based on n-bits controlled CMOS inverters for coarse frequency tuning and diode varactor for fine frequency tuning. The example of a 3 bit digitally controlled oscillator has been implemented in a 0.13μm CMOS process. It can cover a frequency tuning of 1.28-2.6 GHz and thus can support the different standards of 2G, 3G, 4G and future 5G wireless systems. The fabricated LC-VCO occupies a small active area of only (54 × 59)μm2. The phase noise is -87 dBc/Hz @ 1MHz with a power consumption less than 4mW at a supply of 1.1V.

In modern electronic systems, PLLs are widely used for frequency synthesis applications. PLLs have a mixed analog-digital nature, which makes difficult to characterize its overall non-linear behavior using general theory of feedback system. To simulate the transient behavior of the PLL often the circuit level simulator is used. The frequency divider circuit separates the loop in low and high frequency parts leading to a small sampling time and a high simulation time, which are major technological bottlenecks using behavioral or transistor level models. In this paper, electrical simulations of an arbitrary ordered PLL operating with a voltage switched charge pump (VSCP) are performed. By simulating each block of the VSCP-PLL within the loop using transistor level model, the results were used to setup macroscopic parameters within the Event-Driven model. The Event-Driven simulation efficiently characterizes the off-locking transient domain in a very short time. The Event-Driven simulations are validated by transistor level simulations of arbitrary ordered integer-N VSCP-PLL designed in Cadence (Virtuoso) using CMOS technologies (130nm and 65nm).

This article presents the design and implementation of a multi-stage radio-frequency (RF) passive polyphase filter (PPF). The layout parasitics and mismatch which deteriorate significantly the RF filter performance are analyzed and modeled. To reduce this parasitic degradation, a novel optimal layout technique is proposed. It is based on reproducing the same optimized PPF stage layout for the different stages while the desired bandwidth is ensured due to an optimal sizing of the inter-stages connections. This approach has been validated with on chip measurements. Using the proposed techniques more than 55 dB of image rejection over the [1.5; 3.3] GHz bandwidth is demonstrated while achieving zero power consumption and small silicon area in 130nm CMOS technology.

This paper presents a built-in tuning technique in radiofrequency receivers using on-chip polyphase filters. Auto-calibration of the filter resistance values, based on Design-Of-Experiment (DOE) methodology, is proposed. This approach investigates process and temperature monitoring of the frequency band, the image-rejection-ratio (IRR) and the I/Q-accuracy resulting in robust and low-cost solutions.

A low cost and low power frequency synthesizer Based on IEEE 802.15.4 specification using an optimized open-loop modulator is presented for Frequency Shift Keying modulation applications. The fully integrated synthesizer (0.166mm2) is implemented in a 0.28μm CMOS technology with 2.5V supply voltage. Measurements results of PLL lock time, open-loop frequency drift and demodulated signal are presented.

The temperature dependence of the I/sub C/(V/sub BE/) relationship can be characterised by two parameters: E/sub G/ and X/sub TI/. The classical method to extract these parameters consists in a "best fitting" from measured V/sub BE/(T) values, using least square algorithm at constant collector current. This method involves an accurate measurement of Y/sub BE/ voltage and an accurate value of the operating temperature. We propose in this paper, a configurable test structure dedicated to the extraction of temperature dependence of I/sub c/(V/sub BE/) characteristic for BJT designed with bipolar or BiCMOS processes. This allows a direct measurement of die temperature and consequently an accurate measurement of V/sub BE/(T). First, the classical extraction method is explained. Then, the implementation techniques of the new method are discussed, the improvement of the design is presented.