This paper describes the defect coverage evaluation of memory testing algorithms. Realistic CMOS defects were extracted from a 2/spl times/2 SRAM layout using an IFA tool, and circuit simulations were performed to measure the defect coverages of the eleven memory testing algorithms.

This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with three parameters, which include the fault coverage upper bound, UB, the fault coverage lower bound, LB, and the rate of fault coverage change, /spl alpha/. The fault coverages using three different testing scenarios, which are no DFT, scan, iddq testing, are predicted using circuit design information, such as gate count, I/O count, and FF count. These parameters are often readily available at the early stage of VLSI design. Finally, the composite fault coverage is estimated by combining different fault coverages. Experimental result showed a 1.9% model estimation error with a given circuit information in the early design.

The manufacturing of high-quality and reliable semiconductor memories is very important. Many memory testing algorithms have been proposed to improve the quality of semiconductor memories by screening out different memory functional faults. However, the relationships between memory function fault types and the types of defects which cause the functional faults are not well understood. Therefore, the effectiveness of memory testing algorithms based on the functional fault models cannot be realistically determined. This paper evaluates the effectiveness of the memory testing algorithms based on the defect coverage by comparing the defect coverage of known memory testing algorithms and the functional fault coverage of the same testing algorithms using the same defect statistics. The experimental results show that the differences among the defect coverage of the 11 memory testing algorithms other than checkerboard and sliding diagonal tests were not significant as previously believed using memory functional fault coverage as the coverage metric.

This paper proposes a rest cost prediction model which estimates the cost of lC testing in a manufacturing environment. The model predicts chip testing cost and quality of test using a set of circuit manufacturing parameters. The objective is to use these circuit parameters which are available at the early stage of the design cycle to determine and optimize manufacturing test cost.

This paper describes an ASIC yield model based on the CMOS bridge fault model. The model predicts defect sensitive area early in the design cycle as a function of number of gates and nets.