In resource-constrained edge computing, the execution efficiency of workflow applications is significantly affected by bandwidth contention, especially during data transmissions between dependent tasks. However, existing workflow scheduling studies often struggle to optimize transmission delay effectively, whereas bandwidth slicing offers promising potential by leveraging the dynamic nature of bandwidth resources. To address this issue, we propose Workflow Scheduling with Dynamic Bandwidth Slicing (WSDBS), a novel scheduling algorithm that integrates bandwidth slicing into the workflow execution process. By introducing a dual-prediction strategy, WSDBS estimates the availability of both computational and bandwidth resources on servers, facilitating efficient task scheduling decisions under transmission uncertainty. Moreover, a novel transmission urgency metric is developed, which is derived from both link load and transmission criticality. This metric guides bandwidth slicing for the dynamic allocation of server-side bandwidth resources, ultimately alleviating contention among concurrent transmissions. Extensive experiments based on real-world Alibaba cluster traces show that WSDBS consistently improves scheduling efficiency, reducing the average makespan by 10.87%-14.44% over state-of-the-art baselines. These results validate its effectiveness in alleviating bandwidth contention and improving scheduling performance in edge computing environments.

An efficient multi-rate Low-Density Parity-Check Convolutional Code decoder will be present in this paper. We will introduce layered decoding algorithm into LDPC-CC decoding. Simulation results shows that our method can achieve better performance than the original brief propagation algorithm with less processors. Besides a new ASIC architecture which adopt proposed algorithm and can support all code rate (1/2, 2/3, 3/4, 4/5) of the LDPC-CC code in IEEE 1901 is proposed. Based on SMIC 130 nm CMOS process, our decoder attaints a maximum throughput of 333.3 Mb/s at 200 MHz. The core area is 3.55 mm2with 10 processors. The average power consumption is 262 mW at code rate 4/5 and 200 MHz. The VLSI result shows that our decoder is both memory efficient and area efficient.

A highly-parallel LDPC decoder architecture for 10Gbase-T applications is designed in this paper. Firstly, we reduce the routing complexity and corresponding power consumption by the proposed decoder architecture based on single routing networks. Secondly, the proposed architecture is designed with pipelined layered scheduling and multi-block parallel decoding, which improves operation speed and removes pipeline stalls in conventional highly-parallel layered scheduling. Thirdly, we trade off between hardware cost and throughput by a digit-serial data-path. Fourthly, an efficient early-termination circuit suitable for layered decoding is designed. The decoder is implemented in 130nm 1P8M CMOS process. The core area is 18.4mm2with 14% reduction, and the decoding throughput is 9.48Gbps operating at 278MHz and 5 iterations. The tested power consumption is 774mW at 1.2V and 80MHz.