Demo Data from EDBT 2026 / reviewers in the wild / expert
Andrei B. Khlopotine
dblp:81/1351
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2015
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 67% Parallel and multicore computing · 33% | |
| Theoretical computer science
1 paper |
Computational geometry · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › layout verification
design rule checking |
0.2 | 1 | 2013 | A Variant of Parallel Plane Sweep Algorithm for Multicore Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Parallel and multicore computing
parallel algorithms |
0.2 | 1 | 2013 | A Variant of Parallel Plane Sweep Algorithm for Multicore Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Electronic design automation
physical design |
0.2 | 1 | 2013 | A Variant of Parallel Plane Sweep Algorithm for Multicore Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Computational geometry
plane sweep |
0.0 | 1 | 2013 | A Variant of Parallel Plane Sweep Algorithm for Multicore Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Methods — techniques the papers use, named apart from their topics
parallel plane sweep · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2015 | Optimized Parallel Label Propagation Based Community Detection on the Intel(R) Xeon Phi(TM) ArchitectureabstractComplex systems such as social, biological and information networks, characterized by millions to billions of sub-entities and relationships between them are best represented by graphs. A distinguishing feature of such complex systems is the self-organization into dense clusters called communities. Detecting such communities in massive graphs is critical to the understanding of such complex systems. However community detection is non-trivial and is expensive due to a vast number of computations needed to fully realize the underlying relationships. While a number of near-exact and heuristic algorithms is available for community detection, parallelizing such algorithms to fully leverage the advantages of parallel hardware is still a challenging problem. Most presently available approaches attempt to optimize run-time complexities by scaling original serial community detection algorithms. Graph algorithms in general and existing community detection algorithms in particular are known for not being commensurate with linear scalability on parallel systems. Therefore, there is a need for a combination of high-performance software and a hardware platform that would support efficient parallel graph processing with respect to community detection. We present an Intel® Xeon Phi Label Propagation algorithm (PLPA) variant of community detection algorithm based on label propagation (LP). Our algorithm was tuned for the Intel® Xeon Phi platform a novel architecture that provides 50+ physical cores with simultaneous multithreading. We outline Phi architecture advantages and limitations for PLPA and massive graph processing in general. We present test results of running our algorithm on large real-world networks while achieving near linear speedups and improving the quality of the detected communities. We also analyze possibilities of processing massive networks that cannot fully fit in a Phi memory and hence we extend our initial solution to a modified PLPA (PLPA-M). Andrei B. Khlopotine, Arun V. Sathanur, Vikram Jandhyala |
SBAC-PAD | 1 |
| 2013 | A Variant of Parallel Plane Sweep Algorithm for Multicore SystemsabstractParallel algorithms used in Very Large Scale Integration physical design bring significant challenges for their efficient and effective design and implementation. The rectangle intersection problem is a subset of the plane sweep problem, a topic of computational geometry and a component in design rule checking, parasitic resistance-capacitance extraction, and mask processing flows. A variant of a plane sweep algorithm that is embarrassingly parallel and therefore easily scalable on multicore machines and clusters, while exceeding the best-known parallel plane sweep algorithms on real-world tests, is presented in this letter. Andrei B. Khlopotine, Vikram Jandhyala, Desmond Kirkpatrick |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |