Demo Data from EDBT 2026 / reviewers in the wild / expert
K. N. Ramganesh
dblp:81/167
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 81% Hardware reliability and fault tolerance · 19% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.0 | 1 | 2004 | Cutting Metastability Using Aperture Transformation · IEEE Trans. Computers 2004 |
Integrated circuit design
metastability |
0.0 | 1 | 2004 | Cutting Metastability Using Aperture Transformation · IEEE Trans. Computers 2004 |
Hardware reliability and fault tolerance
soft errors |
0.0 | 1 | 2004 | Cutting Metastability Using Aperture Transformation · IEEE Trans. Computers 2004 |
Methods — techniques the papers use, named apart from their topics
runt-free schmitt trigger · 0.0detection/compensation with set&clear controls · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | Cutting Metastability Using Aperture TransformationabstractAperture transformation reduces metastability by trading unsafe edge arrival times with control signal metastability. We improve this further by providing 1) a new runt-free Schmitt trigger-based hardening technique using a controlled clock signal and 2) a new detection/compensation technique that overwrites controlled-clock metastability using set&clear controls. Pradeep Varma, B. S. Panwar, K. N. Ramganesh |
IEEE Trans. Computers | 3 |