Moving data between various components of a system is fast becoming the performance bottleneck in digital design today. This is especially true in high-throughput, memory-intensive applications, like those in multimedia and video processing. With improved fabrication technology, the capacities of application-specific integrated circuits (ASICs) that implement these digital systems are increasing as well. Higher levels of design abstraction are used to prevent the design process from becoming untenable. High-level synthesis (HLS) is one such level of abstraction. We present Midas, an HLS system for ASIC design that treats the data produced and used by a system very differently from any previous HLS system. Midas uses a novel model for HLS centered around data-transfers (DTs), instead of operations as is more traditional. Midas also incorporates floorplanning information within the main HLS flow. The consideration of data-transfers and floorplanning during synthesis allows Midas to design architectures whose storage units and execution units show a close temporal and spatial integration. Data is stored near where it is produced and used. DTs happen over short distances instead of long ones. The total effect is better utilization of internal DT bandwidth on the ASIC.

We presen t a new model for formulating the classic HLS sub-problems: scheduling, allocation, and binding. The model is unique in its use of data-transfers as the basic entity in syn thesis. A data transfer represents the movement of one instance of data and con tains the operation sourcing the data and all the operations using it. Our model compels the storage architecture of the design to be optimized concurren tly with the execution unit. We ha ve built a high-level syn thesis system, Midas, based on our data transfer model. Midas generates designs with smaller storage and data transfer requirements than other HLS systems.

We apply High Level Synthesis (HLS) to the design of FPGA based computing systems. HLS allows for a level of design space exploration unrealizable with Register Transfer Level (RTL) techniques. The use of HLS tools allow designers to prototype their designs with high quality results and fast turn around times. Our design flow makes use of Synopsys Behavioral Compiler (BC) followed by logic synthesis to map designs onto the Altera RIPP10 board. We illustrate our approach with a case study: the design of a DTMF receiver from a high-level behavioral description down to implementation on the RIPP10 board. We were able to design working hardware, meet our delay constraints and achieve 90% utilization of the available FPGAs. The final design had approximately 90000 gate equivalents.

Modern digital systems move and process vast amounts of data. Designing good ASIC architectures for these systems requires efficient data routing and storage. A high-level synthesis (HLS) system must consider spatial aspects of the architecture it synthesizes to achieve this. In this paper, we discuss using floorplanning information in the main HLS flow. Our HLS system, Midas, uses two floorplanners and formulates HLS using a data-transfer model. Midas synthesizes architectures whose data storage and transfer subsystems are spatially integrated with its execution unit. Midas also generates a high-level floorplan for the architecture, which contains the shapes and coordinates of its components and global routing channel specifications for its buses. Our experiments comparing Midas's architectures to those generated by a HLS system that does not use the data-transfer model or floorplanning show that Midas's architectures are smaller and yet allow for large amounts of simultaneous data mo...