We propose an automatic wafer defect maps detection method based on unsupervised learning. There is no need for human labeling, and similar defect clusters are identified automatically without human intervention. As a result, the process is less error-prone. Whenever the wafer test result of a WUT is available, it can be compared immediately with existing clusters. If the wafer map matches one of the known defect patterns, then RCA can be done efficiently.

Wafer map defect pattern recognition is valuable for root cause analysis and yield learning. Most of the previous studies on defect pattern recognition are based on supervised machine learning, in which labeled wafer maps are used to train a machine learning model for automatic classification. Some problems arise in this approach. First, there may be misclassification in the original labeled data, which makes it difficult to establish an accurate prediction model. Secondly, defect patterns that are not defined before will not be classified correctly. In this paper, we proposed a semi-supervised framework to deal with these problems. Labeled wafer maps are first used to train a prediction model, with likely misclassified data excluded. The prediction model is then used to classify unlabeled data. The remaining data that cannot be properly classified are then sent to an unsupervised learning algorithm to extract more defect patterns with enhanced labeling techniques. This proposed approach is validated with TSMC 811K database, in which we are able to define five new defect pattern types. Experimental results show that total 14 defect types can be recognized with overall accuracy of 94.37%.

In-memory computing (IMC) architecture has been considered as an alternative for overcoming the memory wall of von-Neumann computing architecture. Various IMC memories using 8T static random access memory (SRAM) cell have been reported. Some of them, the memory array can provide SRAM and ternary content addressable memory (TCAM) function. In this paper, a March-like test algorithm is proposed, which requires 10 × 2pRead/Write operations, (2q+ 4m) Compare operation, and (2r+1+ 4m) Erase operations to cover simple SRAM faults and TCAM Comparison faults, for an IMC 8T SRAM providing 2p×w-bit SRAM and m× 2q−1-bit TCAM, where p = q+r and m = 2r×w.

Due to the rapid technology scaling and increasing program/erase cycling, the raw bit error rate (RBER) in NAND flash memory keeps increasing rapidly. Conventional error correction codes (ECCs) with stronger protection capability are usually equipped for all flash pages as a solution to maintain the mandatory yield and reliability levels. However, the growth of RBER induced by increasing P/E cycles will lead to uneven distribution of errors. Applying uniform ECC protection capability for all flash pages might incur unnecessary hardware and latency overhead. Moreover, the overlong ECC check bits might be stored in two different flash pages. Therefore, two flash reads are required to retrieve a codeword. In this paper, ECC caching (E3C) techniques are proposed to cure these drawbacks of conventional uniform protection techniques. The main idea is to upgrade the ECC protection levels for flash pages when their correction slack is below the specified threshold. According to experimental results, we can enhance the reliability of flash memories significantly with negligible hardware cost.

By analyzing the fault behaviors of conventional flash memory fault models, two new concise fault types are proposed: the 1-safe fault and the 0-safe fault. For a 1(0)-safe fault, if logic 1(0) is programmed into the faulty cell, the effect of the fault can be masked. Data shaping (DS) and the page address remapping (PAR) techniques are used to increase the masking probability. DS manipulates the data patterns so that they can be written into the flash pages safely. PAR scrambles the logical-to-physical address mapping for data words and buffer words. Since the effect of a fault is masked for a large proportion of faulty cells, the burden on the error-correction code (ECC) is reduced, as is the number of incorporated redundancies. A novel test-and-repair flow is proposed that uses DS and PAR and corresponding hardware architectures are also developed. A simulator is used to evaluate the hardware overhead, the repair rate, the yield, and the reliability. The experimental results show that these measures are significantly improved with an almost negligible hardware overhead.

Content addressable memory (CAM) is widely used in the systems with the need of parallel search. The testing of CAM is more difficult than that of random access memory (RAM) due to the complicated function of CAM. Similar to the testing of RAM, the testing of CAM should cover the cell array and peripheral circuits. In this paper, we propose a March-like test, March-PCL, for detecting the stuck-open faults (SOFs) of the priority address encoder of CAMs. As the best of our knowledge, this is the first word to discuss the testing of SOFs of the priority address encoder of CAMs. The March-PCL requires 4N Write and 4N Compare operations to cover 100% SOFs.

TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.

Rnv8T nonvolatile SRAM combines conventional SRAM and resistive RAM to provide both fast access speed and data retention. Traditional test methods for conventional SRAM or resistive RAM are not suitable for nonvolatile SRAM. This paper analyzes the defective behavior of the Rnv8T nonvolatile SRAM based on defect injection and simulation. Simulation results showed that the inject defects caused stuck-at faults and transition faults which escaped from conventional March tests. Based-on the defective behavior and circuit operations, a straight forward test algorithm is proposed to detect the escaped faults.

This paper proposes a cost-effective TAP-controlled serialized compressed scan architecture (SCSA) design to support known-good-die (KGD) test, known-good-stack (KGS) test and post-bond test in the 3D stacked ICs (3D-SICs) configuration. Additionally, a serialized compressed signal generator (SCSG) design is also developed of the proposed scheme to generate the corresponding controlled signals for SCSA to ensure the test cost reduction. Experimental results and comparisons show that the proposed scheme can effectively achieve the good performance in test pin count and test time reduction with little extra hardware overhead penalty.

Given the critical role of motion estimation (ME) in a video coder, testing such a module is of priority concern. While focusing on the testing of ME in a video coding system, this work presents an error detection and data recovery (EDDR) design, based on the residue-and-quotient (RQ) code, to embed into ME for video coding testing applications. An error in processing elements (PEs), i.e. key components of a ME, can be detected and recovered effectively by using the proposed EDDR design. Experimental results indicate that the proposed EDDR design for ME testing can detect errors and recover data with an acceptable area overhead and timing penalty. Importantly, the proposed EDDR design performs satisfactorily in terms of throughput and reliability for ME testing applications.

The JPEG 2000 image compression standard is designed for a broad range of data compression applications. The discrete wavelet transformation (DWT), central to the signal analysis and important in the JPEG 2000, is quite susceptible to computer-induced errors. The errors can be spread to many output transform coefficients if the DWT is implemented by using lifting scheme. This paper proposes an efficient error tolerance scheme (ETS) to detect errors occurring in DWT. A pipeline-based DWT structure is also developed in this paper to speed up the error detection process. The proposed ETS design uses weighting sums of the DWT coefficients at the output compared with an equivalent check value derived from the input-data. With the proposed ETS design, the errors introduced at DWT can be effectively detected. Additionally, the results of error detection can be further analyzed and evaluated to show the capability of error tolerance. Some standard images are used as test samples to verify the feasibility of the proposed ETS design. Experimental results and comparisons show that the proposed ETS has good performance in error detection time and error tolerance capability.

This paper develops a built-in self-detection/correction (BISDC) architecture for motion estimation computing arrays (MECAs). Based on the error detection/correction concepts of biresidue codes, any single error in each processing element in an MECA can be effectively detected and corrected online using the proposed BISD and built-in self-correction circuits. Performance analysis and evaluation demonstrate that the proposed BISDC architecture performs well in error detection and correction with minor area overhead and timing penalty.

This paper proposes the design of a current-mode resonator with complex coefficients based on fully-balanced operational transconductance amplifiers (FBOTAs) and grounded capacitors. The proposed current-mode resonator can be used in a quadrature /spl Delta//spl Sigma/ modulation for digital radio or can be employed as a foundation to realize high-order complex filters with in cascade or leapfrog for wireless local area network (LAN) applications. For realizing the current-mode resonator herein, only two grounded capacitors as passive elements are required. Thus, the proposed current-mode resonator is suitable for the integrated circuit realization. Chip design and measured results are presented to verify the theoretical analysis.