In this paper a novel pipelining approach applicable to Winograd Fourier transforms is presented. The novel approach makes use of reconfigurable multiplier blocks to implement the real multipliers required for the transform as well as sharing the hardware resources among additions. The additions are realized using modified forms of butterfly circuits. The novel approach is tested on a 5-point Winograd Fourier transform and the circuit area and power dissipation of the design are estimated using an in-house power estimation tool and compared to the state-of-the-rt approaches.

This paper describes a novel idea to identify the total number of red blood cells (RBCs) as well as their location in a Giemsa stained thin blood film image. This work is being undertaken as a part of developing an automated malaria parasite detection system by scanning a photograph of thin blood film in order to evaluate the parasitemia of the blood. Not only will this method eliminates the segmentation procedures that are normally used to segment the cells in the microscopic image, but also avoids any image pre-processing to deal with non uniform illumination prior to cell detection. The method utilizes basic knowledge on cell structure and brightness of the components due to Giemsa staining of the sample and detects and locates the RBCs in the image.

This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the image-rejection-ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

This paper deals with and details the design and implementation of a low-power; hardware-efficient adaptive self-calibrating image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Hybrid strength-reduced and re-scheduled data-flow, low-power implementation of the adaptive self-calibration algorithm is developed and its efficiency is demonstrated through simulation case studies. A behavioral and structural model is developed in Matlab as well as a low-level architectural design in VHDL providing valuable test benches for the performance measures undertaken on the detailed algorithms and structures.

This paper provides an overview of the sources and effects of the RF impairments limiting and rendering the performance of the future wireless communication transceivers costly as well as hindering their wide-spread use in commercial products. As transmission bandwidths and carrier frequencies increase effect of these impairments worsen. This paper studies and presents analytical evaluations of the performance degradation due to the RF impairments in terms of bit-error-rate and image rejection ratio. The paper also give highlights of the various aspects of the research carried out in mitigating the effects of these impairments primarily in the digital signal processing domain at the baseband as well as providing low-complexity hardware implementations of such algorithms incorporating a number of power and area saving techniques

Global navigation satellite system (GNSS) receivers require solutions that are compact, cheap and low-power, in order to enable their widespread proliferation into consumer products. Furthermore, interoperability of GNSS with non-navigation systems, especially communication systems will gain importance in providing the value added services in a variety of sectors, providing seamless quality of service for users. An important step into the market for Galileo is the timely availability of these hybrid multi-mode terminals for consumer applications. However, receiver architectures that are amenable to high-levels of integration will inevitably suffer from RF impairments hindering their easy widespread use in commercial products. This paper studies and presents analytical evaluations of the performance degradation due to the RF impairments and develops algorithms that can compensate for them in the DSP domain at the base band with complexity-reduced hardware overheads, hence, paving the way for low-power, highly integrated multi-mode GNSS receivers

In this paper, we propose a low-complexity architecture for the implementation of adaptive IQ-imbalance compensation in quadrature zero-IF receivers. Our blind IQ-compensation scheme jointly compensates for IQ phase and gain errors without the need for test/pilot tones. The proposed architecture employs early-termination of the iteration process; this enables the powering-down of the parts of the adaptive algorithm thereby saving power. The complexity, in terms of power-down efficiency is evaluated and shows a reduction by 37-50 % for 32-PSK and 37-58 % for 64-QAM modulated signals

This paper presents a new design approach for a rail-to-rail bulk-driven input stage using a standard single-well (n-well in this paper) CMOS technology. This input stage can provide nearly constant transconductance and constant slew rate over the entire input common-mode voltage, operating with a wide supply voltage ranging from sub 1-volt (VT0+ 3VDSsat) to the maximum allowed for the CMOS process, as well as preventing latch-up

This paper describes an MPEG (moving pictures expert group) audio layer II - LFE (lower frequency extension) bit-stream processor targeting DAB (digital audio broadcasting) receivers that will handle the decoding of the frames in a computationally efficient manner to provide a synthesis sub-band filter with the reconstructed sub-band samples. Focus is given to the frequency sample reconstruction part, which handles the re-quantization and re-scaling of the samples once the necessary information is extracted from the frame. The comparison to a direct implementation of the frequency sample reconstruction block is carried out to prove increased computational efficiency

An adaptive self-calibrating image rejection receiver is described, containing a modified weaver image rejection mixer and a digital image rejection processor (DIRP). The blind source-separation-based DIRP eliminates the I/Q errors improving the image rejection ratio (IRR) without the need for trimming or use of power-hungry discrete components. Hardware complexity is minimal, requiring only two complex-coefficients; hence it can be easily integrated into the signal processing path of any receiver. Simulation results show that the proposed approach achieves 75-97 dB of IRR.

Phase and gain mismatches between the I and Q analog signal processing paths of a quadrature receiver are responsible for the generation of image signals which limit the dynamic range of a practical receiver. We analyse the effects of these mismatches and propose a low-complexity blind adaptive algorithm to minimize this problem. The proposed solution is based on two, 2-tap adaptive filters, arranged in an adaptive noise canceller (ANC) set-up. The algorithm lends itself to efficient real-time implementation with minimal increase in modulator complexity.

Two novel effective-fourth-order (eighth-order) resonator based MASH (MultistAge noise SHaping) bandpass /spl Sigma/-/spl Delta/ modulators are introduced at the behavioural level and subsequently examined by simulations utilising the ALTA SPW environment. The considered bandpass configurations have in their loop filter a cascade of standard second-order resonator structures in order to achieve appropriate noise shaping. The quantisation noise in each stage is suppressed by feeding the error of each section into the input of the following stage. It is demonstrated in this paper that the quadruple effective-first-order cascade configuration has significantly better performance as well as conforming more closely with theory in comparison with the effective-second-order effective-second-order cascade. The superior performance of the former can be attributed to the cumulative effect of the multi-bit outputs as well as the presence of more notch filters.

This paper addresses a new approach for the design of multiband filters with step like magnitude responses and extremely flat, weighted passbands down to /spl mu/dBs. Our new technique can also be used for the multiband stepwise approximation of arbitrary filter magnitude responses with precise transition band control. One marked advantage of the technique is that our basic building blocks are the modified polyphase (W) filters. The points of transition from one flat-top to another, namely the multiple transition bands of our filter are completely free of cross-over oscillations. One other advantage of this technique is that we are not confined to employing IIRs only. To this end perfect reconstruction FIR filters can also be used. In both the FIR and IIR cases our technique is general purpose and works for both real and complex valued filter coefficient cases.

This paper presents a design technique for high fidelity multistage decimation filters based on polyphase and decimator structures, catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Converter (ADC) applications in excess of 15 bit resolution. The resulting filter coefficients are constrained to the required bit length using a "bit flipping algorithm". This technique is comparatively presented through an example of a cascaded decimation filter, designed for a 20-bit resolution ADC and compared to other approximation methods. The coefficients and frequency responses of the cascaded filter are reported.>

A MININET "station" acts as a user concentrator into the MININET word-switched network where each word (of up to 16 bits) entering a network "port" is mapped into a single packet for immediate transmission through the network. The stations maintain highly transparent "virtual connections" between user devices. Among the important requirements for MININET are that, under saturation conditions, the communication resources of the network be shared fairly between the user devices and that the network possesses very short end-to-end propagation delays. The design of a station meeting these requirements, capable of processing over one million packets per second, is described. Its architecture is based on special-purpose processors which are functionally distributed. The biggest design challenge was to minimize the processing delay in the node while avoiding potential blockages and remaining fair. The final solution has been to use a master arbiter, which looks at the readiness of the ports and channels in conjunction with connection, routing, and flow control information. The station management entities reside in a general-purpose microcomputer. These monitor and modify the operation of the high-speed processors, establish virtual connections, and support the routing algorithm.

This paper describes a control protocol for high-speed transfers between transceivers in a data communication system. One particularly suitable application of current topical interest would be to control lines linking nodes in a local area packet-switching system. The protocol applies for fixed-length data packets which must ultimately be received at their destination in sequence. With these specifications, a set of rules which is easy to implement in practice is established. The result is a packet interlock method of numbering packet transmissions and jumping back to retransmit a series of packets under error conditions. Problems associated with multiple errors, dummy packets, initial synchronization and resynchronization are investigated and found to be readily overcome by the proposed protocol.