This paper will discuss why and how the University of Applied Sciences, Darmstadt/Germany will identify core competences of bachelor's degrees in Electronic Engineering and develop specially tailored lifelong learning programmes for non-traditional students. These programmes will enable highly qualified master craftsmen, solely educated to the level of master craftsmen, to successfully participate in the existing Master of Science in Electronic Engineering programme. Furthermore, this paper will present the initial results obtained from a pilot project group.

Digital correlation techniques are used in photon correlation spectroscopy (PCS) experiments to gain information about the diffusion coefficient and thereby the size and distribution of submicron particle structures in fluid media. A new multichannel single chip correlator architecture has been developed, implemented on a FPGA device as a HW/SW partitioned system. A fast hardware front-end combined with a highly optimised, hardware accelerated softcore processor allows the simultaneous processing of up to 32 input channels, each with a time dynamic range 1013. This paper outlines the fundamental algorithmic concepts, the actual correlator implementation as well as the HW/SW design consideration to find an optimal trade-off between system resources and application requirements.

Design methodologies for high performance Direct Digital Fre-quen--cy Synthesizers (DDFS) are described. Traditional look-up tab-les (LUT) for sine and co-sine are merged with CORDIC-inter-po---la--tion into a hybrid architecture. This implements DDFS-sys-tems with high resolution without being specific to a particular tar-get technology. Amplitude constants were obtained from ma-the-matical trigonometric functions of the IEEE math_real pack-age. These constants were then written via simulation of a VHDL model into a fully synthesizable package. Systematic and detailed studies varying the synthesizers inherent parameters lead to a design optimum of the LUT/CORDIC-ra-tio, which mini-mizes power and silicon area for a given clock frequency.

Signal delay, chip area, and power dissipation are conflicting criteria for designing high-performance VLSI MOS circuits. Global optimization of transistor sizes in digital CMOS logic circuits with the design tool multiobjective gate-level optimization (MOGLO) is described. Analytical models for the design objectives are presented, and algorithms are discussed. Different techniques were combined to solve the circuit optimization problem with low computational costs. Precise gate-level delay models guarantee meaningful results, especially for high-speed logic circuits.>