The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers (CONV) can no longer improve the performance of wide dynamic gates for the future technologies. In this paper, we propose an adaptive keeper technique called rate sensing keeper (RSK) that enables faster switching and tracks the variation across different process corners. It can switch upto 1.9× faster (for 20 legs) than CONV and can scale upto 32 legs as against 20 legs for CONV in a 130-nm 1.2-V process. The delay tracking is within 8% across the different process corners. We demonstrate the circuit operation of RSK using a 32 × 8 register file implemented in an industrial 130-nm 1.2-V CMOS process. The performance of individual dynamic logic gates are also evaluated on chip for various keeper techniques. We show that the RSK technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR).

Transistor variability has emerged as one of the important constraints in Nano-CMOS circuit design. The ever decreasing device feature size with CMOS scaling, has resulted in an increasing uncertainty in predicting the exact device behaviour. The issue of variability needs to be addressed across the entire hierarchy of integrated circuits - optimization of process and device technology to yield minimal variability, robust circuit and system design architectures for variability aware design, and CAD tools to unify these two domains. The traditional variability modeling and CAD techniques address the problem in one of the two domains. We propose a unified framework to bridge the gap between technology CAD and design CAD. This framework enables one to directly relate the variation in circuit metrics such as speed, static power and dynamic power to the underlying semiconductor process parameters such as implant dose, annealing temperature etc. The proposed methodology is validated through rigorous simulations at the process, device and circuit level, incorporating various statistical techniques. A few examples will be presented to elaborate the significance of the proposed modeling methodology and its utility in the Nano CMOS design flow. In addition to being an important utility in the circuit design flow, the methodology will also help the foundries by providing a visibility on the impact of unit processes on the eventual circuit characteristics. This in turn can help in a systematic and optimized process monitoring in the foundries.

A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130 nm CMOS technology.

We determine the optimal allocation of power between the analog and digital sections of an RF receiver, while meeting the BER constraint. Unlike conventional RF receiver designs, we treat the SNR at the output of the analog front end (SNRAD) as a design parameter rather than a specification to arrive at this optimal allocation. We first determine the relationship of the SNRAD to the resolution and operating frequency of the digital section. We then use power models for the analog and digital sections to solve the power minimization problem. As an example, we consider a 802.15.4 compliant low-IF receiver operating at 2.4 GHz in 0.13μm technology with 1.2 V power supply. We find that the overall receiver power is minimized by having the analog front end provide an SNR of 1.3dB and the ADC and the digital section operate at 1-bit resolution with 18MHz sampling frequency while achieving a power dissipation of 7mW.

A high precision 16-bit readout circuit for gas sensor interface is realized in 0.13μm CMOS technology. The front end signal conditioning circuit comprises a low power resistance-to-time period converter with subthreshold operation of transistors. The time-period proportional to the transducer output is digitized using a counter based frequency-to-digital conversion (FDC) technique. In order to handle the sensor signal with a dynamic range of 160dB, subranging technique is employed to provide feedback to front end circuit interfacing the sensor. While the 3 MSBs of 16-bit word restrict the input frequency to FDC between 1MHz and 10MHz, the 13-bit counter operates on this signal to provide a worst case resolution of 0.4%. The power consumption of the readout circuit is 366μW from a 1.2V supply.

Double Gate(DG)FET is one of the most promising technologies for sub-50 nm transistor design. Various attempts have been made to exploit this newly emerging technology in electronic circuits [1, 2]. Threshold voltage of a double gate MOSFET can be varied by varying the bias on the back gate [1]. In this paper we propose a variable gain differential amplifier with current mirror load utilizing this property. Also it is shown that the saturation voltage of the differential amplifier varies with the varying back gate bias of the DGFETs. The variable gain differential amplifier has been used to propose a variable hysteresis voltage schmitt trigger, the hysteresis voltage of which can be varied without the help of external circuitry and only by varying backgate bias of the DGFETs. The nature of variation of hysteresis voltage with varying backgate bias of the transistors is also investigated.

A generalized methodology for modeling the effects of process variations on circuit delay performance is proposed by directly relating the variations in process parameters to variations in delay metric of a digital circuit. The 2-input nand gate is used as a library element for 65 nm gate length technology, whose delay is extensively characterized by mixed-mode simulations. This information is then used in a general-purpose circuit simulator SEQUEL, by incorporating appropriate templates for the nand gate library. A 4-bit times 4-bit Wallace tree multiplier circuit, consisting of about 300 2-input nand gates, is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized by an extensive Monte Carlo analysis. To extend this methodology for a generic technology library with a variety of library elements, modeling of nand gate delays by response surface methodology (RSM), in terms of process parameters, is carried out using design of experiments (DOE). A simple piecewise quadratic model, based on the least squares method (LSM), is proposed for one-parameter variation to address significant cubic effects observed in the delay response function. Then, a hybrid model for gate delays is generated by superimposing the interaction terms of DOE-RSM model upon the quadratic model of one-parameter variation to address the generalized case of simultaneous variations in multiple process parameters. The proposed methodology has been demonstrated for nand gate library with 266 gates, and the simplicity and generality of the approach make it equally applicable to a large library of cells for both statistical timing analysis and statistical circuit simulation at the gate level

Process, device, and mixed-mode (device/circuit) simulation-based approach is presented for 0.1-/spl mu/m gate length CMOS technology optimization and sensitivity analysis. The disposable spacer-based 0.1-/spl mu/m NMOS and PMOS transistors with excellent short channel characteristics are designed using process and device simulations. The implant-dose sensitivity of the device parameters around the nominal value are estimated. The halo implant and super steep retrograde channel implant dose fluctuations are found to have a profound effect on device characteristics. It is shown that the mixed-mode device/circuit simulation can be used as an excellent tool to connect the circuit delay sensitivity to underlying process parameters. The simulation results demonstrate that the relation between circuit and process parameters is highly nonlinear for the deep submicron technology.