Emojis in texts provide lots of additional information in sentiment analysis. Previous implicit sentiment analysis models have primarily treated emojis as unique tokens or deleted them directly, and thus have ignored the explicit sentiment information inside emojis. Considering the different relationships between emoji descriptions and texts, we propose a pre-training Bidirectional Encoder Representations from Transformers (BERT) with emojis (BEMOJI) for Chinese and English sentiment analysis. At the pre-training stage, we pre-train BEMOJI by predicting the emoji descriptions from the corresponding texts via prompt learning. At the fine-tuning stage, we propose a fusion layer to fuse text representations and emoji descriptions into fused representations. These representations are used to predict text sentiment orientations. Experimental results show that BEMOJI gets the highest accuracy (91.41% and 93.36%), Macro-precision (91.30% and 92.85%), Macro-recall (90.66% and 93.65%) and Macro-F1-measure (90.95% and 93.15%) on the Chinese and English datasets. The performance of BEMOJI is 29.92% and 24.60% higher than emoji-based methods on average on Chinese and English datasets, respectively. Meanwhile, the performance of BEMOJI is 3.76% and 5.81% higher than transformer-based methods on average on Chinese and English datasets, respectively. The ablation study verifies that the emoji descriptions and fusion layer play a crucial role in BEMOJI. Besides, the robustness study illustrates that BEMOJI achieves comparable results with BERT on four sentiment analysis tasks without emojis, which means BEMOJI is a very robust model. Finally, the case study shows that BEMOJI can output more reasonable emojis than BERT.

Recommendation systems are an effective solution to deal with information overload, particularly in the e-commerce sector, in which sequential recommendation is extensively utilized. Sequential recommendations aim to acquire users’ interests and provide accurate recommendations by analyzing users’ historical interaction sequences. To improve recommendation performance, it is vital to take into account the long- and short-term interests of users. Despite significant advancements in this domain, some issues need to be addressed. Conventional sequential recommendation models typically express each item with a uniform embedding, ignoring evolutionary patterns among item attributes, such as category, brand, and price. Moreover, these models often model users’ long- and short-term interests independently, failing to adequately address the issues of interest drift and short-term interest evolution. This study proposes a new model, the Feature-aware Long-Short Interest Evolution Network (FLSIE), to address the above-mentioned issues. Specifically, the model uses explicit feature embedding to represent item attribute information and employs a two-dimensional (2D) attention mechanism to distinguish the significance of individual features in a specific item and the relevance of each item in the interaction sequence. Furthermore, to avoid the issue of interest drift, the model employs a long-term interest guidance mechanism to enhance the representation of short-term interest and adopts a gated recurrent unit with attentional update gate to model the dynamic evolution of users’ short-term interest. Experimental results indicate that our presented model outperforms existing methods on three real-world datasets.

Target-oriented opinion word extraction (TOWE) is critical in aspect-based sentiment analysis. It aims at extracting opinion words that are related to aspect terms. Existing TOWE approaches primarily focused on explicit or implicit target aspects. However, few methods dealt with them simultaneously. For compensating this limitation, this study proposes a dual-cell recurrent network (DCRN) that combines aspect term extraction (ATE) and target-oriented opinion word extraction. The DCRN model is trained and evaluated on global fields, including explicit and implicit target aspects. Empirical results demonstrate that the proposed DCRN model outperforms existing methods by an average of 4.90% on the SemEva114–16 datasets. Furthermore, the DCRN model achieves higher Macro-F1 values than the IOG model on the Restaurant 14–16 datasets by 8.97%, 7.90 %, and 8.70 %, respectively. These results indicate that the DCRN model significantly improves the performance of TOWE and exhibits robust generalization capabilities.

Misinformation has brought great challenges to the government and network media in social networks. To clarify the influences of behaviors of the network media, government, and netizen on misinformation propagation, a large number of influence parameters are proposed for the three participants. Then, a tripartite evolutionary game model for misinformation propagation is constructed. According to the proposed game model, the expected payoffs of three participants are analyzed when they adopt different strategies. The evolutionary stabilities of the game model are also analyzed theoretically. Finally, the impacts of different parameters on expected payoffs of three participants are analyzed experimentally. Meanwhile, coping strategies of three participants under different conditions are given. The experimental results show that the proposed tripartite evolutionary game model can properly describe the influence of network media, government, and netizen on misinformation propagation.

The Hyperlink-Induced Topic Search (HITS) algorithm developed by Jon Kleinberg made use of the link structure of the web pages on the Web in order to discover and rank web pages being relevant to a particular topic. However it only took account of the hyperlink structure, while completely excluded contents of web pages, and it ignored the fact that degrees of the importance of many hyperlinks on the Web may be different. In this paper, to overcome the topic drifts, we proposed a novel page ranking algorithm combining the hyperlink with the triadic closure theory by considering fully the Vector Space Model (VSM) and the TrustRank algorithm. The method firstly computed the relevance between two randomly arbitrary web pages based on web page topic similarity and common reference degree. Then, by using that model as a point of reference, a new adjacency matrix was constructed to iteratively calculate the authority and hub values of web pages. Next, we calculated the trust-degree for each web page in the basic set by the trust-score algorithm. Finally, the score for each web page is computed by linearly merging the authority and the trust-degree. In our experiments, we used five classic HITS-based algorithms to compare with our proposed page ranking algorithm-PCTHITS (Web Page Topic Similarity, Common Reference Degree, Trust-degree) algorithm. The experimental results demonstrated that our proposed algorithm outperform the other four classic improved algorithms and HITS algorithm.

Infrequent errors, such as unwanted glitches occurring once every a few seconds in silicon tuners, are very costly to capture in production due to long test time by the nature of the errors. The paper presents a novel scheme that reduces the test time from a few seconds to a few tens milliseconds. The scheme has been implemented to test millions of silicon TV tuners, and field defects caused by the glitches were successfully eliminated.

Jitter test in production is notorious for its long test time and the challenge of accuracy verification. Among various types of jitter, Random Jitter (RJ) is most challenging to test on Automatic Test Equipment (ATE) because of its randomness. To be considered as a favorable jitter test in production for multi-gigabit devices, the RJ needs to be measured with sub-picosecond accuracy and the whole test time is expected to be in a few tens of milliseconds. However, no known solutions meet these criteria to our best knowledge. In this paper, we present a systematic solution for multiple Giga-bit-per-second (Gbps) Transmitter (TX) jitter testing on ATE. Our undersampling-based solution extracts jitter either from edge histograms in time domain or from the jitter spectrum in frequency domain. Both approaches provide a RJ precision better than ±0.5ps and are capable of finishing the whole TX test within 100ms. We have verified the solution with data rates up to 6Gbps and applied it in mass production.

In our previous publication (Cai, et. al., 2005), we demonstrated the ability to generate the proper mix of jitter on ATE to enable the jitter tolerance test for 1.5/3Gbps SATA applications. Obviously this is not the only challenge for performing this test on ATE. Jitter tolerance compliance test for SerDes calls for validation of bit-error-rate (BER) down to the 10-12or lower. This requirement deemed this test to be extremely time-consuming, which normally takes more than an hour (assuming running 1013bits for 10-12BER level guaranteed). While in the ATE world every test is measured in seconds or even in milliseconds; it is obviously impractical to adopt this test directly. In this paper we demonstrate a new technique to perform the jitter tolerance test >1000 times faster. The technique of course involves extrapolation from the higher BER region down to the 10-12level for the compliance test, but the challenge that we faced in getting the extrapolation is very different from the conventional transmitter jitter measurement world. We present a new mathematical model suitable to reason about this extrapolation process

FPGAs have witnessed an increased use of dedicated communication interfaces. With their increased use, it is becoming critical to test and properly characterize all such interfaces. Bit error rate (BER) characteristic is one of the basic measures of the performance of any digital communication system. We propose a scheme for BER testing in FPGAs, which exhibits a few orders of magnitude speedup compared to traditional software simulation methods. In this scheme, we include a novel implementation of an additive white Gaussian noise (AWGN) generator with high speed and high accuracy for channel emulator. Compared to traditional BER test products, our scheme can test BER under different noise conditions. The whole system is implemented as an IP core, suitable for a single FPGA device.