EDBT 2026 Demo / reviewers in the wild / expert
Jiamin Li 0008
dblp:81/3437-8
· DBLP profile ↗
4ranked-venue papers
0as first author
4since 2021 · last 2026
0000-0002-3566-7855ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 4 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | A 40-nm Resilient MLC RRAM Macro with Self-Referenced Time-Based Readout and 3-Bit Interleaved ECC Achieving 0.22 pJ/bit Read Energy
Zhen Kong, Yida Liang, Humiao Li, Yida Li 0004, Jiamin Li 0008, Longyang Lin |
ISCAS | 6 |
| 2026 | Mitigating Conductance Drift via In-Situ Calibration for Reliable RRAM-Based CIM Edge Inference
Zhen Kong, Weirong Dong, Zhengke Yang, Yida Liang, Jiamin Li 0008, Yida Li 0004, Longyang Lin |
ISCAS | 7 |
| 2026 | A 3-D Connectivity CMOS Ising Machine With 12-Way Toroidal Hexagonal Close-Packed Supply-and-Bulk Injection Locking Oscillators for Combinatorial OptimizationabstractFinding optimal solutions for Combinatorial Optimization (CO) problems is challenging. Compared to power-hungry cryogenic quantum computer and time-consuming classical computer, quantum-inspired Ising machine solves CO problems at room temperature with fast optimization speed, low power consumption, and low cost. Nevertheless, the Ising machine still faces several challenges: digital CMOS Ising machines increase interaction freedom at the cost of greater area and larger processing time; in analog Ising machine, oscillator spins find it hard to differentiate spin states without the assistance of the post-processing algorithm, and latch spins suffer from mismatches. To address these issues, we propose an oscillator-based 3-D CMOS Analog Ising Machine (CAIM) which adopts the 12-way toroidal Hexagonal Close Packed (HCP) structure, Supply-And-Bulk Injection Locking (SABIL), and dual-mode tunable coupler. The toroidal HCP structure exhibits >2 & times; interactions compared to conventional 3-D Ising machine, while SABIL and dual-mode tunable coupler settle oscillators to a bistable ground state 2.2 & times; quicker with an 8.5 & times; wider lock range (within 5 cycles). The proposed CAIM successfully solves 3-D max-cut problems and achieves a normalized Hamiltonian energy of more than 0.98 with a maximum perfect accuracy prevalence (PAP) of 91.67%. Measurement results on a sample random Max-Cut instance demonstrate that CAIM converges to within 1.7% of the reference optimum in 5 cycles. Jiaer Chen, Yingna Huang, Zhong-Qi Li, Han Wu 0003, Longyang Lin, Jiamin Li 0008, Jerald Yoo |
IEEE Trans. Circuits Syst. I Regul. Pap. | 6 |
| 2026 | A Low-Power Speech-Based Depression Recognition Processor With Hierarchical Local-Global NetworkabstractDepression is a critical public health concern characterized by underdiagnosis, often due to stigma, lack of awareness, and reluctance to seek help. Cases of delayed intervention could be alleviated by wearable solutions which enable continuous and unobtrusive monitoring of depression indicators. Compared to electroencephalogram (EEG)-based and video-based depression recognition, speech-based approaches can be performed without deliberate user attention. However, due to the limited accuracy of existing algorithms and constrained resources at edge, performing accurate speech-based depression recognition on wearable platforms remains a challenge. Therefore, to achieve unobtrusive, accurate, and efficient depression recognition at edge, this work presents a hierarchical local–global network (HLG-Net) and optimized processor design for speech-based depression recognition. The proposed HLG-Net integrates convolutional neural networks (CNNs) with multihead attention (MHA) mechanism to simultaneously capture local acoustic features and global utterance-level coherence, enhancing depression stage recognition. For efficient processor design, a cross-layer buffered dataflow is proposed for efficient data handling, reducing data storage by 98.77%. The computing unit (CU) employs layer fusion, operator optimization, and quantization techniques to further improve resource utilization and reduce power consumption while preserving recognition accuracy. System-level low-power techniques such as clock/input gating and near-threshold design for application specific integrated circuit (ASIC) further reduce power consumption. The proposed processor implemented on field-programmable gate array (FPGA) (XC7Z100-2FFG900) achieves the lowest reported mean absolute error (MAE) of 5.13 on AVEC 2014 database. The 180-nm ASIC implementation shows a simulated power consumption of$17.4~\mu $W at 0.4 V. The results demonstrate the feasibility of accurate and efficient speech-based depression recognition on wearables. Yuxing Zhi, Weirong Dong, Huaijun Wang, Longyang Lin, Jiamin Li 0008 |
IEEE Trans. Very Large Scale Integr. Syst. | 6 |