The demand for higher data rates, capacity and better quality-of-service is constantly growing for home networks. Therefore, there is a pressing need for efficient use of wireless network resources. In this context, the application of cognitive radio principles that enable network nodes to characterize their environment and control their resources based on the acquired knowledge, is the prominent solution for next generation home networks. In this paper we present an architecture and a prototype implementation based on these principles. The proposed system is able to autonomously optimize the performance of network nodes in a dynamic environment according to the goals, restrictions and policy regulations formulated by network stakeholders. The obtained results show the momentous and suitability of the cognitive framework for home networking.

The proposed demonstration is based on commodity 802.11 wireless cards and a low cost 2.4GHz sniffing device and shows how current WLAN based networks can benefit from spectrum awareness and dynamic access to the assigned band. The demonstrator presents a solution to problems in current wireless networks, like inefficient radio spectrum usage and limited ability to withstand interferences. The presented spectrum-aware radio management framework flexibly negotiates transmission parameters based on spectrum usage and application requirements and opportunistically utilizes available bandwidth. A key feature of this demonstrator is the fact that it breaks the traditional fixed channel bandwidth limitation and enables dynamic bandwidth allocation according to the needs of applications. It continuously monitors the assigned spectrum, tracks application behaviour, and dynamically adapts to the radio environment, such as interference and competition. Furthermore, a cross-media roaming mechanism is provided in the framework to support seamless handovers within and between radio technologies. Our enhancements are transparent to upper layer applications and will automatically benefit any software using network resources. The presented demonstrator uses wireless video streaming in a typical household scenario to illustrate the benefits without changes to the multimedia applications.

There have been many proposals for constructing routing tables for distributed hash tables (DHT). They can be classified into two groups: A) those that assume that the peers are uniformly randomly distributed in the identifier space, and B) those that allow order-preserving hash functions that lead to a skewed peer distribution in the identifier space. Good solutions for group A have been known for many years. However, DHTs in group A are limited to use randomized hashing and therefore, queries over whole identifier ranges thus do not scale. Group B can handle such queries easily. However, it is more difficult to connect the peers such that the resulting topology provides efficient routing, small routing tables, and balanced routing load. We present an elegant new solution to construct an efficient DHT for group B. Our main idea is to decouple the identifier space from the routing topology. In consequence, our DHT allows arbitrarily skewed peer distributions in the identifier space and does not require the overhead of sampling. Furthermore, the table construction is cheap and does not require active replacement of lost routing entries. To evaluate the performance of routing cost and table construction under high churn, we built an efficient simulator. Using the right data structures, we can easily process the state of over one million peers in RAM.

Present mobile devices often support multiple communication technologies. If software developers want to control the configuration or monitor the characteristics of active links their applications will have to use different programming interfaces for each technology and supported platform. We propose an architecture for a unified link-layer API (ULLA) to abstract common metrics and introduce a single interface for retrieving link-layer information. ULLA offers a flexible query interface and a powerful notification mechanism that enable applications to become link-aware. Additionally, special attention was paid to keep the framework extendible for emerging networking technologies. We have implemented prototypes for a Linux notebook and a Windows CL PDA in order to prove the feasibility of the approach. Memory footprint, query duration, and power consumption tests show that ULLA can also be deployed on mobile, resource limited devices

Distributed Shared Memory (DSM) architectures are attractive to execute high performance parallel applications. Made up of a large number of components, these architectures have however a high probability of failure. We propose a protocol to tolerate node failures in cache-based DSM architectures. The proposed solution is based on backward error recovery and consists of an extension to the existing coherence protocol to manage data used by processors for the computation and recovery data used for fault tolerance. This approach can be applied to both Cache Only Memory Architectures (COMA) and Shared Virtual Memory (SVM) systems. The implementation of the protocol in a COMA architecture has been evaluated by simulation. The protocol has also been implemented in an SVM system on a network of workstations. Both simulation results and measurements show that our solution is efficient and scalable.

Traditionally, cache coherence in multiprocessors has been maintained in hardware. However, the cost-effectiveness of hardwired protocols is questionable. Virtual Shared Memory systems have highlighted the many advantages of software-implemented protocols, albeit at a performance price. The performance gap is narrowed by hybrid systems with the addition of hardware support for fine-grain sharing. We have developed a software protocol for a COMA (Cache-Only Memory Architecture). We call the system SC-COMA for Software-Controlled COMA, to emphasize that the protocol engine is emulated by software executed on the main processor. Contrary to user-level protocols, the software handling coherence events in SC-COMA runs in sub-kernel mode, transparently providing the same services to applications as a hardware counterpart. The software emulation layer has been written and we compare SC-COMA to an idealized hardware COMA through detailed simulations. Our results show that SC-COMA is competitive. On systems with 32 processors, it achieves a slowdown of 11-56% with respect to its hardware counterpart, across a range of applications and memory pressures. SC-COMA scales well, up to 32 nodes. A study on the impact of faster processors on SC-COMA's relative performance indicates a consistent improvement, but with a limitation due to the loosely-integrated design. We conclude that SC-COMA is a viable solution to easily transform networks of workstations into powerful multiprocessors.

Due to the increasing number of their components, Scalable Shared Memory Multiprocessors (SSMMs) have a very high probability of experiencing failures. Tolerating node failures therefore becomes very important for these architectures particularly if they must be used for long-running computations. In this paper, we show that the class of Cache Only Memory Architectures (COMA) are good candidates for building fault-tolerant SSMMs. A backward error recovery strategy can be implemented without significant hardware modification to previously proposed COMA by exploiting their standard replication mechanisms and extending the coherence protocol to transparently manage recovery data. Evaluation of the proposed fault-tolerant COMA is based on execution driven simulations using some of the Splash applications. We show that, for the simulated architecture, the performance degradation caused by fault-tolerance mechanisms varies from 5% in the best case to 35% in the worst case. The standard memory behavior is only slightly perturbed. Moreover, results also show that the proposed scheme preserves the architecture scalability and that the memory overhead remains low for parallel applications using mostly shared data.

This paper focuses on the problem of fault tolerance in shared memory multiprocessors, and describes an architecture designed for transparently tolerating processor failures. The Recoverable Shared Memory (RSM) is the novel component of this architecture, providing a hardware supported backward error recovery mechanism which minimizes the propagation of recovery when a processor fails. The RSM permits a shared memory multiprocessor to be constructed using standard caches and cache coherence protocols, and does not require any changes to be made to applications software. The performance of the recovery scheme supported by the RSM is evaluated and compared with other schemes that have been proposed for fault tolerant shared memory multiprocessors. The performance study has been conducted by simulation using address traces collected from real parallel applications.

COMAs (Cache Only Memory Architectures) are an interesting class of large scale shared memory multiprocessors. They extend the concepts of cache memories and shared virtual memory by using the local memories of the nodes as large caches for a single shared address space. Due to their large number of components, these architectures are particularly susceptible to hardware failures and so fault tolerance mechanisms have to be introduced to ensure a high availability. In this paper, we propose an implementation of backward error recovery in a COMA which minimizes performance degradation and requires little hardware modifications. This implementation uses the features of a COMA to implement a stable storage abstraction using the standard memories of the architecture. Recovery data are replicated and mixed with current data in node memories both of which are managed in a transparent way using an extended coherence protocol.