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R. J. F. de Vries

dblp:81/3771 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Performance modeling and evaluation · 56% Interconnection networks and networks-on-chip · 44%
Computer networks
1 paper
Routing and switching · 100%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › switch architecture
ATM switch
0.011992
Cell Loss Performance of the Gauss ATM Switch · INFOCOM 1992
Performance modeling and evaluation › queueing models
cell loss probability
0.011992
Cell Loss Performance of the Gauss ATM Switch · INFOCOM 1992
Interconnection networks and networks-on-chip › switch architecture
output-buffered switching
0.011992
Cell Loss Performance of the Gauss ATM Switch · INFOCOM 1992
Performance modeling and evaluation
queueing models
0.011992
Cell Loss Performance of the Gauss ATM Switch · INFOCOM 1992
Routing and switching › switch architecture
nonblocking switch design
0.011990
Gauss: A Simple High Performance Switch Architecture for ATM · SIGCOMM 1990
Routing and switching
switch architecture
0.011990
Gauss: A Simple High Performance Switch Architecture for ATM · SIGCOMM 1990
Performance modeling and evaluation
analytical modeling
0.011992
Cell Loss Performance of the Gauss ATM Switch · INFOCOM 1992

Methods — techniques the papers use, named apart from their topics

modular switch design · 0.0performance comparison · 0.0analytical modeling · 0.0
YearPublicationVenuePosition
1992 Cell Loss Performance of the Gauss ATM Switch
abstract
The authors present a performance study of the Gauss asynchronous transfer mode (ATM) switch with respect to cell loss. The Gauss switch is a recently proposed, high-performance, output buffered ATM switch that can easily be implemented. In general, if an ATM switch suffers from cell loss, the exact behavior of this cell loss as a function of parameters such as load, traffic business, internal speed, etc., has to be known. The study focuses on cell loss in the Gauss switch due to its reduced internal speed. Analytical results for the cell loss probability are provided and compared to corresponding quantities for the well-known knockout switch. The comparison shows that the Gauss switch yields significantly smaller cell loss probabilities than the knockout switch.>
E. Aanen, Hans van den Berg, R. J. F. de Vries
INFOCOM3
1990 Gauss: A Simple High Performance Switch Architecture for ATM
abstract
Broadband ISDN will use the Asynchronous Transfer Mode (ATM) as its basic switching, multiplexing and transmission technique. ATM is very flexible and promising, nevertheless, it requires high-performance switching hardware. The ATM Switching Element (ASE) proposed in this paper, called the Gauss ASE, can meet ATM requirements. Using traffic observations and a number of well known design principles the Gauss ASE gets a number of favorable properties, for example the Gauss ASE is nonblocking and has minimum delay and variance of delay. The ASE is kept modular so that it can easily grow towards a large single stage switching fabric using only two types of Integrated Circuits.
R. J. F. de Vries
SIGCOMM1