Forsilicon carbide (SiC) MOSFET applications, it has been a constant challenge to address the trade-off among drain-source voltage slew rate (dv${}_{\mathbf {ds}}$/dt), drain-source voltage spike, and turn-off loss. The existing active gate drivers (AGDs) have not considered the influence of dynamically varying drain current, resulting in increased turn-off loss and voltage spike. To address this issue, this paper proposes a cross-cycle dynamic active gate driver (CDAGD) that features constant (dv${}_{\mathbf {ds}}$/dt)${}_{\mathbf {max}}$and spike under dynamic drain current. By deriving the quantitative relationship among the gate current,drain current, (dv${}_{\mathbf {ds}}$/dt)${}_{\mathbf {max}}$, and voltage spike, the optimal gate currents in different switching stages are determined. Furthermore, the CDAGD incorporates a cross-cycle gate current regulator (CCGCR) to generate the required gate currents in different stages, and a dynamic switching timing controller (DSTC) to locate the optimal timing of the stages. With the CDAGD providing the optimal gate current, the turn-off loss is minimized with reduceddv${}_{\mathbf {ds}}$/dtand spike.Fabricated in a$0.18\mu $m BCD process, the CDAGD chip achieves a maximum reduction in turn-off loss of 72.2% and 37.9% compared with the conventional gate driver (CGD) and AGD under varying drain current. A 45.9% reduction in turn-off time is also achieved with the proposed gate driver.

Highly repetitive structures in IC, such as SRAM cells typically require extremely low failure ratio, making traditional Monte Carlo analysis extremely time consuming. Furthermore, the “curse of dimensionality” has become a major challenge for existing high-sigma yield analysis techniques. Thus, we propose a “sampling-training-substitution-verification” (STSV) yield analysis framework, which utilizes machine learning (ML) techniques to accelerate yield analysis in high-sigma and high-dimensional scenarios, effectively addresses the “curse of dimensionality.” In our framework, least absolute shrinkage and selection operator (Lasso) regression is adopted to substitute the mapping from process parameters to circuit performance, achieving high accuracy, and generalization. The model is adaptive for both low- and high-dimensional scenarios since the dimensional sparsity is achieved by$l1$regularization. In addition, important process parameters can be identified by sparse feature weights of the Lasso model, which is of assistance for yield optimization. Compared with existing yield analysis techniques, the Lasso-based STSV framework offers great saving in a simulation program with integrated circuit emphasis (SPICE) cost, is attractive in high-dimensional demands.

For boost converter operating in the discontinuous conduction mode (DCM), feedback and feedforward compensators are widely used to improve the converter performance. However, it is relatively difficult to optimize load transient response (LoTR), line transient response (LiTR), and reference tracking speed (RTS) simultaneously, since the optimizations require different compensators that are incompatible. In order to solve the issue, a superposed compensation strategy is proposed in this paper, which consists of a feedback compensator and two feedforward compensators. Each compensator is tuned according to an objective transfer function, which optimizes LoTR, LiTR, and RTS. The outputs are summed as duty cycle according to the linear superposition principle. Compatibility of the compensators is improved by designing the feedforward compensators to adapt to the feedback compensator. Furthermore, based on the closed-loop model, design rules for the objective transfer functions are given to minimize the influences of the sample-and-hold effect and calculation delay, which are intrinsic in a digital controller. Finally, converter's LoTR, LiTR, and RTS are simultaneously optimized, which is proven by closed-loop magnitude-frequency plots, state trajectory analyses, and experimental results.

In a sensorless predictive current controlled boost converter, parameterizing the inductor plays an important role in controller performance. In this paper, a solution for inductor parameters online identification is investigated. A small-signal injection strategy is proposed to create a transient state, and convergence problem of inductance identification in steady state can be avoided. Then, a charge balance current observer (CBCO), derived from capacitor current charging balance concept, is adopted to estimate the inductor current for inductance identification. Since inductance is not used in CBCO, current estimation is not affected by inductance identification error. Because of rank-deficient problem, instead of identifying inductor parasitic resistance solely, the inductor equivalent parasitic resistance is derived. By applying it into the conventional current observer for current control loop, the accuracy of current estimation can still be guaranteed since more parasitic effects are included. To improve the accuracy of inductance identification, a load identification method is investigated. Furthermore, the effect of the equivalent series resistance of output capacitor on the proposed algorithm is analyzed. Finally, its effectiveness is verified by experimental results.

Off-chip memory security has become a prime concern in embedded computing systems due to the requirement of storing a large amount of potentially sensitive information in them. Existing solutions have performance imperfection because of their deployment of hash tree or unaffordable on-chip memory overhead. In this paper, we propose an efficient off-chip memory protection mechanism based on Advanced Encryption Standard - Galois/Counter Mode (AES-GCM) to provide both confidentiality and integrity protection for data and programs transferred from processor to off-chip memory in embedded computing systems. Our proposal is a novel memory protection mechanism: in order to ensure security and minimize on-chip memory overhead, AES-GCM hardware engine is running and dynamically switching between two modes, one mode for processing data and programs (DP mode), the other mode for processing the cryptographic parameter of IV (IV mode). It can resist well-known physical attacks, including replay attacks, relocation attacks and spoofing attacks. We demonstrate that our memory protection mechanism incurs as little as 1.56% on-chip memory overhead and has an average performance decline of about 9.0%.