When pseudorandom patterns generated by a linear feedback shift register (LFSR) are used as test stimuli, there is always a concern about the linear dependencies within the sequence of patterns. It is possible for these linear dependencies to preclude a specific test pattern from being present in the sequence of applied patterns. These dependencies and ways to calculate their effects on a particular test are discussed, with the goal of developing the means of analyzing a digital circuit which is connected to a source of pseudorandom patterns to determine whether or not linear dependencies are encountered by a particular connection.>

This paper describes the performance of the Self-Test System used in the production of circuit modules for the new line of mainframes, the ES/9000 series. The system supports pseudorandom patterns generated and applied in a self-test mode from within the module, as well as control and pseudorandom stimuli and response compression through the IjO pins. Simulation-based diagnostics are used to generate repair actions to specific micro-nets, with an associated confidence level. Modules (containing roughly 500,000 gates) are being verified in under 3 minutes, with diagnosis of failing modules resulting in the isolation of a fault with 5 minutes of on-line time, followed by 11.7 minutes of off-line analysis.

The circumstances under which a partitioning of a task with a polynomial complexity will result in an overall reduction of its execution time are analyzed. It is assumed that the task executor is sequential in nature, namely it can execute only one task at a time. Since partitioning of a task into smaller subtasks will, most probably, result in subtask overlap, there is a risk that a given partitioning scheme will yield an increase in its overall execution time. Formulas are derived to test the effectiveness of any proposed partitioning scheme. In the case of multiple partitioning options, the best one can be easily obtained. One of the possible tasks that this analysis is applicable to is the test generation of digital circuits with a uniprocessor.>

The consequences of the similarity transformation between the transition matrix of a linear cellular automaton (CA) and that of a linear feedback shift register (LFSR) are explored. It is shown that the bit sequence from a stage of a CA is identical to that from the LFSR found by the similarity transformation. The concept of discrete algorithms of a binary polynomial is introduced and used with an operational calculus to calculate the phase shift between the bit sequences emitted by different stages of a linear CA. The simulation of hybrid 90/150 CA done during the course of this work leads to some conjectures about the realizability of cellular automata exhibiting maximum length sequences with null and cyclic boundary conditions.>

When pseudorandom patterns generated by a linear feedback shift register (LFSR) are used as test stimuli, there is always a concern about the linear dependencies within the sequence of patterns. It is possible for these linear dependencies to prevent a specific test pattern from being present in the sequence of applied patterns. These dependencies and ways to calculate their effects on a particular test are discussed. Using the analysis procedures outlined, it is possible to construct the sampling polynomial that describes the connection between a fault under test and the STUMPS structure. This sampling polynomial can then be analyzed to determine if the connection contains any linear dependencies. If a linear dependency is present in the connection, and if it prevents a required test from being presented to the fault under test, the connections between the fault under test and the STUMPS structure must be changed.>

Parallel pseudorandom sequences for use in built-in test are discussed. The two-dimensional nature of these sequences-makes it natural to consider the resulting binary arrays. Some of the desired properties of such arrays are discussed, as well as some of the problems. Generators for such arrays are described. A conventional LFSR with parallel output is shown to be a poor choice for such a generator. Several compact generators are described, which are shown to be compromises between complexity and varying degrees of implementation of the desired properties in the resulting sequences. One of the compact generators produces sequences which have the desired properties for built-in tests.

The testing of large logic networks with random patterns is examined. Work by previous workers for single faults is extended to a class of multiple fault situations. Not only is the problem of fault detection in the presence of nonmasking multiple faults treated, but the question of distinguishing between them is also examined. It is shown that a test that merely exposes each fault has a high probability of distinguishing between the faults. The relationships between quality, diagnostic resolution, and random pattern test length are developed. The results have application to self-test schemes that use random patterns as stimuli.

A major problem in self testing with random inputs is verification of the test quality, i.e., the computation of the fault coverage. The brute-force approach of using full-fault simulation does not seem attractive because of the logic structure volume, and the CPU time encountered. A new approach is therefore necessary. This paper describes a new analytical method of computing the fault coverage that is fast compared with simulation. If the fault coverage falls below a certain threshold, it is possible to identify the ``random-pattern-resistant'' faults, modify the logic to make them easy to detect, and thus, increase the fault coverage of the random test.