An experimental multifrequency receiver for recognition of digitally encoded multifrequency signaling was designed, constructed and tested. The receiver is based on a quadrature detection technique that consists of digital demodulation followed by second-order, lowpass digital filtering. The post filtering processing produces an estimate of the amplitude of each of the six multifrequency tones and provides suitable information for thresholding and timing measurements. The receiver performs correctly even when subjected to severe environmental conditions including an analog signal range of 23 dB, 10 ms signal interruptions ('hits') and 20 ms signal spacings. The receiver's operation demonstrates the robustness of the digital signal processing techniques employed. The design of the receiver exploits the use of subsampling techniques to increase the efficiency of the hardware through greater multiplexing. When using subsampling, 128 multifrequency receivers with 16-bit words are realized with 6.5 dual-in-line packages per receiver; commercial TTL logic circuits, a 4-bit serial-parallel pipeline multiplier circuit, serial data and a 16.384 MHz clock are assumed.

A differential current-switching circuit configuration is proposed for implementing threshold logic, and a first-order statistical analysis of the configuration is described. The configuration is intended for use within functional digital integrated circuits. It can be realized in a form that is fully compatible with conventional emitter-coupled logic (ECL).

Multiplication is an essential operation in digital signalprocessing algorithms. In such applications the organization of a multiplier typically ranges from parallel array to serial-parallel pipeline, with many intermediate possibilities. In this concise paper, the parallel array and serial-parallel pipeline organizations are compared on the basis of the power dissipation needed to achieve a specified multiplication rate. The first-order comparison is intended to serve as a preliminary aid in the design of custom integrated multiplier circuits. The comparison illuminates the differences in circuit technology appropriate for the two organizations. It also indicates that, insofar as custom integrated circuit design is concerned, design parameters other than power dissipation are likely to be the dominant considerations in choosing a multiplier organization.

An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described. The two's complement multiplication is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit, and the signs of all the partial product bits are positive.

An algorithm is described which generates the set of representative functions of the negation and/or permutation of variables and negation of the function (NPN) equivalence classes of unate Boolean functions. The algorithm is based upon integer programming techniques. The set of representative functions for the NPN equivalence classes of unate functions of six or fewer variables was obtained using this algorithm. The set of pseudothreshold functions of six or fewer variables was also tabulated by using this algorithm as a basis.

Optimal networks consisting of NOR-OR gates (each gate produces the NOR and/or the OR of its inputs) are tabulated for all Boolean functions of three variables. Optimality is defined as minimizing first the number of gates and then the number of interconnections. The optimal networks were synthesized for each Boolean function by using an integer programming synthesis technique.

Upper and lower bounds are derived for the number of pseudothreshold functions of n variables. (Pseudothershold logic is a generalization of threshold logic.) It is shown that a lower bound on the number of pseudothreshold functions P(n) of exactly n variables realized by zero-free structures is The number of pseudothreshold functions Q(n) of n variables realized by nontrivial structures is bounded by It is also proven that is a lower bound on the number of positive functions of exactly n variables.

The number of threshold functions of eight variables is counted by ILLIAC II, the computer of the University of Illinois. Sets of optimum weights of majority elements realizing these functions also are investigated. Actually, canonical positive self-dual threshold functions of nine variables are investigated instead of directly investigating threshold functions of eight variables because it is easier to deal with them. The number and optimum weights of threshold functions of eight variables are easily obtained from these functions of nine variables and their realization.