In this paper, a computer-aided design system for CMOS VLSI circuit hot-carrier reliability estimation and redesign is presented. The system first simulates a circuit to determine the critical transistors that are most susceptible to hot-carrier effects (HCEs). It then estimates the impact of HCE on circuit performance and employs a combination of design modification strategies to eliminate HCE-induced performance degradation. Two criteria are used to evaluate HCE degradation. The first criterion is the estimation of local damage in each transistor, which indicates the possibility of failure of individual devices. The second criterion is the global degradation of the circuit, namely the increase of delay in digital circuits. If either criterion exceeds a user-specified limit, several alternative circuit redesign strategies can be chosen by the user from a suggested menu. Based on this choice, the system will automatically redesign the critical parts of the circuit to improve circuit performance. The advantages and disadvantages of these alternative redesign strategies are also compared.

In this paper, a new approach is presented for estimating the hot-carrier induced degradation in MOS transistors in VLSI circuits. With the decrease in feature size, many long-term reliability issues, such as HCE (Hot-Carrier Effect), TDDB (Time-Dependent Dielectric Breakdown), etc., can no longer be ignored during the design process. In this work we mainly concentrate on HCE; however, the approach can be applied to investigate other reliability issues. HCE is a long-term reliability issue that is caused by the cumulative effects of all possible inputs on the devices in the circuit over time. Existing techniques use deterministic circuit or timing simulation to estimate HCE and try to predict the age of the design by incorporating device degradation over time. As a result, all HCE simulators are too slow (especially if linked to SPICE-circuit simulators) for large circuits; and even when fast simulation techniques are used, user-specified deterministic input waveforms are needed and, hence, the results can only represent a small sample of operating conditions. In this paper, we propose a probabilistic timing approach. The advantage of probabilistic simulation is that we can explore the cumulative effects of all possible input waveform combinations in one run. The approach has been implemented in a general-purpose simulator and tested on a number of typical examples and benchmarks.>

In this paper a computer-aided design system for CMOS VLSI circuit hot-carrier reliability estimation and redesign is presented. The system first simulates circuits to determine the critical transistors that are most susceptible to hot-carrier effects (HCE); it then estimates the impact of HCE on circuit performance and employs a combination of design modification strategies to eliminate HCE degradation on the performance. The advantages and disadvantages of these alternative designs are also compared.>

An approach for estimating hot-carrier induced degradation in MOS transistor circuits is presented. The approach uses probabilistic timing simulation techniques to estimate the cumulative effects of all possible inputs on hot-carrier effect (HCE) degradation in each transistor in the circuit in a single run rather than using exhaustive or Monte Carlo simulations. The approach has been implemented in a general-purpose simulator and tested on a number of typical examples and benchmarks.>