We describe a mathematical physics approach to electromagnetic information theory. The approach is based on quantum tunnelling theories that are formulated in a ray dynamical phase-space. Starting from a scattering model of waves transmitted across two holographic surfaces, we show that the eigenvalues corresponding to communication modes supported by the surfaces can be approximated as tunnelling rates. The related phase-space calculations provide simplified formulas of degrees of freedom for diversity in the near-field. The approach results in rigorous, physics-based framework for general characterisation of surface communications in free-space and confined environments.

The use of computational electromagnetics (CEM) techniques has greatly advanced nanophotonics. The applications of nanophotonics in turn motivates the development of efficient highly tailored algorithms for specific application domains. In this paper, we will discuss some specific considerations in seeking to advance CEM for nanophotonic design and discovery, with examples drawn from the design of aperiodic nanophotonic structures for on-chip information processing applications.

We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

Routers built around a single-stage crossbar and a centralized scheduler do not scale, and (in practice) do not provide the throughput guarantees that network operators need to make efficient use of their expensive long-haul links. In this paper we consider how optics can be used to scale capacity and reduce power in a router. We start with the promising load-balanced switch architecture proposed by C-S. Chang. This approach eliminates the scheduler, is scalable, and guarantees 100% throughput for a broad class of traffic. But several problems need to be solved to make this architecture practical: (1) Packets can be mis-sequenced, (2) Pathological periodic traffic patterns can make throughput arbitrarily small, (3) The architecture requires a rapidly configuring switch fabric, and (4) It does not work when linecards are missing or have failed. In this paper we solve each problem in turn, and describe new architectures that include our solutions. We motivate our work by designing a 100Tb/s packet-switched router arranged as 640 linecards, each operating at 160Gb/s. We describe two different implementations based on technology available within the next three years.

The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects.

We show that there is a limit to the total number of bits per second,B, of information that can flow in a simple digital electrical interconnection that is set only by the ratio of the lengthlof the interconnection to the total cross-sectional dimensionAof the interconnect wiring—the “aspect ratio” of the interconnection. This limit is largely independent of the details of the design of the electrical lines. The limit is approximatelyB∼BoA/l2bits/s, withBo∼ 1015(bit/s) for high-performance strip lines and cables, ∼1016for small on-chip lines, and ∼1017–1018for equalized lines. Because the limit is scale-invariant, neither growing nor shrinking the system substantially changes the limit. Exceeding this limit requires techniques such as repeatering, coding, and multilevel modulation. Such a limit will become a problem as machines approach Tb/s information bandwidths. The limit will particularly affect architectures in which one processor must talk reasonably directly with many others. We argue that optical interconnects can solve this problem since they avoid the resistive loss physics that gives this limit.

The authors discuss digital optics, a technology for processing, transport, and storage of optical digital information. Digital optics offers both the high temporal bandwidth of fiber communications and the high connectivity and information density of optical imaging. The energy dissipation per bit of communicated information, as well as the chip area dedicated to interconnections, can be significantly lower in optics than in high-speed electronics. This motivates the introduction of parallel optical interconnections through free space in communication-intensive areas of digital information processing such as switching in telecommunications and within multiprocessors. Digital optical circuits can be constructed by cascading two-dimensional planar arrays of optical logic gates interconnected in free space. The state of the art and the trends in digital optical information processing systems for optical logic, optoelectronic interfaces, and optical free-space interconnection systems are reviewed.>