In many DSP applications (image and voice processing), several dBs of SNR loss can be tolerated without noticeable impact on application level performance. For power optimization in such applications, voltage overscaling (VOS) can be used to operate the arithmetic circuitry at or marginally below the critical circuit path delay while incurring tolerable SNR loss due to the resulting periodic errors in computation. In this paper, low cost checksum codes are used for detection and compensation of intermittent errors due to voltage overscaling in linear digital filters. In traditional coding theory, diagnosis of errors is a key problem and incurs significant computation and latency cost. In the proposed approach, low-precision shadow latches are used to identify likely sources of errors due to voltage overscaling to avoid error diagnosis. This allows accurate error compensation with distance-2 checksum codes that are normally good only for error detection but not for correction. Very precise compensation is achieved by distributing the negative of the error value evenly across only the likely erroneous states. This is called guided probabilistic compensation, as compensation is not exact when errors occur simultaneously in more than one state. A feedback controller is used for dynamic voltage overscaling (DVOS) while keeping the error rate in the system within an acceptable range. It is shown that the low cost accurate error compensation allows significant power savings with minimal degradation in system performance (SNR).

Voltage overscaling for power reduction in RF systems has been limited by the need to maintain sufficient overscaling guard bands to ensure that minimum signal quality requirements of the end to end communication link are met. In this paper, we propose error control mechanisms at the symbol (probabilistic symbol remapping) and bit levels (code based correction and feedback) that allow more aggressive voltage overscaling than is possible otherwise. Error control feedback is used to continuously monitor and control the tuning knobs of the front end RF circuitry to trade off signal quality vs. power consumption. Real time image and voice data is used to demonstrate this concept. Significant power savings is achieved using the proposed scheme while maintaining minimum signal quality as required by the wireless communication link.

In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR loss due to the resulting periodic errors in computation. In this paper, the use of checksum codes along with low precision shadow latches for compensating errors induced by voltage overscaling in digital filters is investigated. A PID controller is used for voltage overscaling while keeping the error rate in the system within acceptable range. It is shown that significant power savings can be achieved by the proposed technique.

As channel conditions in wireless communications improve, the noise performance of the baseband DSP processor can be degraded to save power without compromising bit error rate. The degradation of baseband signal noise is achieved by degrading the noise performance (reducing the wordlength and supply voltage) of the various baseband signal processing modules in specific proportions defined by a locus, that ensures minimum overall power consumption for a given channel. In the presence of intra-die process variations, this locus is determined by the delay/leakage parameters of each baseband module. In our approach, a path oscillation test applied to each module is used to select the "best" locus of choice and an EVM driven feedback loop is used to dynamically modulate the wordlength/power consumption of each module as dictated by this locus to minimize power and modulate baseband SNR across a range of channel conditions.

Soft errors due to alpha particles, neutrons and environmental noise are of serious concern in highly scaled CMOS circuits. This mandates the use of error/noise tolerance mechanisms in circuit design. Prior work has addressed error correction and compensation techniques for linear digital systems using checksum codes. However no low-cost checksum based technique is found in the literature for nonlinear digital signal processing systems. The problem of error detection and compensation in nonlinear systems is harder due to difficulties in encoding nonlinear operations and correcting for errors in the same. This paper presents a checksum based technique for error compensation in nonlinear digital filters using the time-freeze linearization method. The technique uses distance-two linearized checksum error detection codes for SNR improvement using probabilistic error compensation instead of deterministic error removal. It is shown that by careful checksum code design, significant filter SNR improvement can be obtained in the presence of soft errors.