This paper presents a data-driven robust control framework for wave energy converters. Unlike traditional model-based approaches that neglect uncertainties, the proposed method uses a data-driven model with polytopic uncertainty identified from experimental data of a Wavestar-type prototype. The control problem is cast as a convex semidefinite program with linear matrix inequalities (LMIs), enabling the synthesis of a robust H2 controller that maximises average energy capture. Numerical results demonstrate that the proposed controller either outperforms or matches passive, reactive, and H-infinity strategies in energy absorption and control efficiency.

This work investigates the application of event-triggered control (ETC) in combination with the linear quadratic regulator (LQR) for discrete-time systems. A methodology is presented that uses an iterative approach to tune the LQR controller and reduces control effort by replacing periodic control with ETC. Lyapunov’s stability theory is applied to design triggering mechanisms and analyse their effects on control design. Using the inverted pendulum on a cart as a reference system, it is demonstrated that proper tuning of the LQR controller and the implementation of an event-based control mechanism can reduce control energy and actuator effort.

In this work, a novel methodology is introduced that employs genetic algorithms to determine the optimal weighting matrices for a linear quadratic regulator controller. A method is presented to construct a multi-objective fitness function that allows one to give prioritisation to energy consumption or other performance metrics, such as rise time, settling time, and steady-state error. To validate the effectiveness of the proposed approach, we conducted simulation studies based on a model of an inverted pendulum on a cart system. The results show a reduction of up to 30.36% in the energy of the controller and a reduction of 20.27% in its maximum value when choosing to prioritise the energy expenditure of the controller over other performance metrics, without significantly compromising the convergence of the system states. The results encompass an effective way of optimising energy expenditure in non-linear controller designs.

Abstract Penetration testing (PT) is a method for assessing and evaluating the security of digital assets by planning, generating, and executing possible attacks that aim to discover and exploit vulnerabilities. In large networks, penetration testing becomes repetitive, complex and resource consuming despite the use of automated tools. This paper investigates reinforcement learning (RL) to make penetration testing more intelligent, targeted, and efficient. The proposed approach called Intelligent Automated Penetration Testing Framework (IAPTF) utilizes model-based RL to automate sequential decision making. Penetration testing tasks are treated as a partially observed Markov decision process (POMDP) which is solved with an external POMDP-solver using different algorithms to identify the most efficient options. A major difficulty encountered was solving large POMDPs resulting from large networks. This was overcome by representing networks hierarchically as a group of clusters and treating each cluster separately. This approach is tested through simulations of networks of various sizes. The results show that IAPTF with hierarchical network modeling outperforms previous approaches as well as human performance in terms of time, number of tested vectors and accuracy, and the advantage increases with the network size. Another advantage of IAPTF is the ease of repetition for retesting similar networks, which is often encountered in real PT. The results suggest that IAPTF is a promising approach to offload work from and ultimately replace human pen testing.

Recent works have been claiming efficient hardware architectures, showing a considerable endeavor to implement chaotic maps in the digital domain. However, there is a critical issue with the chaotic degradation in the digital environment due to its finite numeric precision, that it is still an unsettled topic in the research community. Additionally, less attention has been given to synthesize a methodological approach to how to calculate the exponential function in hardware. In this paper, two novel hardware designs to represent the exponential chaotic map have been suggested. We have employed a perturbation method to avoid the chaotic degradation. 64-bit fixed-point and 32-bit floating-point formats were investigated. Moreover, an approximation of Euler's number by a finite series and the Horner's method have been undertaken to further minimize the proposed hardware. Results show that both proposed hardware architectures consume a fewer number of components. The designed systems present a positive Lyapunov exponent, which suggests a chaotic behavior. Ultimately, the NIST SP 800-22 test, the histogram, and the autocorrelation function show that the new hardware architectures present pseudo-random properties.