Tracking finger movement for natural interaction using hand is commonly studied. For vision-based implementations of finger tracking in virtual reality (VR) application, finger movement is occluded by a handheld device which is necessary for auxiliary input, thus tracking finger movement using cameras is still challenging. Finger tracking controllers using capacitive proximity sensors on the surface are starting to appear. However, research on estimating articulated hand pose from curved capacitance sensing electrodes is still immature. Therefore, we built a prototype with 62 electrodes and recorded training datasets using an optical tracking system. We have introduced 2.5D representation to apply convolutional neural network methods on a capacitive image of the curved surface, and two types of network architectures based on recent achievements in the computer vision field were evaluated with our dataset. We also implemented real-time interactive applications using the prototype and demonstrated the possibility of intuitive interaction using fingers in VR applications.

A programmable battery is a tiny computer that children can use to control motors and other devices by manipulating buttons on the board. Since it is simpler to use than other programming and computational tools for children, no detailed instruction is needed to start playing and designing with it. As a result, children can concentrate on their creative activities related to the projects in the workshops. This design also demonstrates the possibilities of computational tools as playthings for children.

The Programmable Battery is a tiny computer that can control motors, lights, and any devices that use dry batteries. By pressing buttons on the Programmable Battery, the pattern of on and off for the devices is recorded and played back repeatedly. Since it has limited functions but can be programmed easily without a computer, anyone can make their own computational devices anytime and anywhere. In this paper, I introduce the concept of the Programmable Battery and its workshops for elementary school students.

Over many years, the technology of circuit refinement has achieved a tremendous large-scale integration, so that VLSI systems such as many-core VLSI processor have emerged. However, in the huge VLSI systems, various problems such as many communication problems of the VLSI network, clock synchronization of the entire system, and verification of concurrent processing, must be solved in order to realize a dependable parallel system. In this paper, we introduce a parallel architecture with short path communication, featuring a random connection in Small World Network, and present network architecture without global clock using communicative process by CSP synchronization method.

The purpose of this study is (1) to provide information about three-site multipoint distance learning utilizing the high-definition “HyperMirror” and (2) to determine how the video image quality of standard definition and high definition affect distance learning. We carried out distance learning projects twice in 2010, on (a) January 28th [Standard Definition] and (b) February 24th [High Definition], with middle schools in Nara and Kumamoto and the High Energy Accelerator Research Organization, Tsukuba in Japan. The three locations successfully connected using HyperMirror during the projects. Afterwards, a questionnaire survey revealed that image quality was not the sole contributing factor in the overall assessment of HyperMirror. However, it was suggested that easy-to-see figures, pictures, and remote students’ facial expressions were important for students.

Embedded systems have become an essential technology in fields that require electronic control. These technologies must work in real time and have high reliability and low cost. Among them, safety verification of embedded systems is very important in fields related to human life. In addition, as multi-core and multiprocessors have spread, the processing power of the hardware has been improved. As a result, concurrent processing has become necessary. In developing concurrent embedded systems, Communicating Sequential Processes (CSP) is regarded as useful. The purpose of this study is to verify, implement, and evaluate the concurrent sorting algorithm using the characteristics of CSP. In this study, we use two characteristics of CSP: synchronous communication and verification based on the formal method. In addition, we describe the extended improvement concurrent sorting algorithm.

Cellular neural networks (CNN) is a neural network model linked to only neighborhoods. CNN is suited for image processing such as noise reduction and edge detection. Small world cellular neural networks (SWCNN) is a CNN extended by adding a small world link, which is global short-cut. SWCNN has better performance than CNN. One of weak points of SWCNN is fault tolerance. We proposed multiple SWCNN layers in order to improve fault tolerance of SWCNN. However, it is not sufficient because only stop failure is considered. In this paper, we propose stateful reliability counter for triple modular redundancy (stateful RC-TMR) method in order to improve tolerance.

In this paper, we propose a new network drawing tool, which considers the direction of traffic on Autonomous System level (AS-level) networks. Almost all traditional network graph drawing tools consider only the connections between nodes and disregard the direction of traffic. Moreover, these tools tend to draw complicated pictures. The reasons for this are that AS-level network structures are very different to random graphs, and have a short diameter, effective connections, and several hubs. We also propose selection of information, and implement the spring algorithm to regulate the positions of nodes for better understanding and some ideas for AS-level network structures in graphic drawing tools. Information traffic is simulated in an AS-level network topology, with dynamic query scheduling to evaluate whether servers balance load well and are suitably located. Given the complexity of this topology, graphical drawing tools are necessary when depicting such networks. Our new network drawing tool draws simple pictures, and can not only express non-directed graphs, but also traffic with direction on AS-level networks, using valley-free rules proposed by Gao. These rules classify links into three policies which are expressed with different colors and shapes by our tool. Our tool clearly shows the differences between traffic routes with valley-free rules and shortest paths in non-directed graphs.

Recently, the exchange of data has increased with progress in information technology. The capacity of for storing data is also increasing. However, even if the capacity of global storage becomes extremely large, the capacity of local storage is always limited. Moreover, storage of files larger then the available local storage is impossible. This paper discusses use of a network to construct a cheap, high trust and PB class, decentralized storage system using many hundreds of PCs in an educational environment. The performance of this 'large-scale virtual disk' is investigated both during normal operation and in instances of failure.

We have developed a processor development environment C-DASH (C-like Design Automation Shell). C-DASH generates HW (Hardware) and SWDE (Software Development Environment) from a processor definition file. To use C-DASH, each user must install C-DASH into local PC. When developing a processor as a team there is often a problem of file consistency, such as when another developer changes the same files you have. To solve this problem a collaborative development environment is required. This paper describes the implementation of a server side ubiquitous codesign environment for an ISA simulator. A server side codesign environment makes it unnecessary to install C-DASH onto local hosts, and makes codesign environment into device independent, and collaborative development becomes easier. A developer can upload a processor definition file via a web browser and develop an ISA (Instruction Set Architecture) simulator.

We have developed a distributed search engine, called Cooperative Search Engine (CSE), in order to retrieve fresh information. In CSE, a local search engine located in each Web server makes an index of local pages. A meta search server integrates these local search engines in order to realize a global search engine. This meta server is a single point of failure in CSE. So, we propose redundancy of meta search servers in order to increase availability of CSE. In this paper, we describe the reliable architecture of CSE and its evaluations.

We have developed distributed search engine, called cooperative search engine (CSE), in order to retrieve fresh information. In CSE, a local search engine located in each Web server makes an index of local pages. And, a meta search server integrates these local search engines in order to realize a global search engine. This meta server is single point of failure in CSE. We propose redundancy, of meta search servers in order to increase availability of CSE. In this paper, we describe reliable architecture of CSE and its evaluations.

We have developed a distributed search engine, called cooperative search engine (CSE), in order to retrieve fresh information. In CSE, a local search engine located in each Web server makes an index of local pages. A meta search server integrates these local search engines in order to realize a global search engine. In such a way, the communication delay occurs at retrieval time. So, it is thought to be difficult to search quickly. However we have developed several speedup techniques in order to realize real time retrieval. In addition, the meta server is a single point of failure in CSE. So, we propose redundancy of meta search servers in order to increase availability of CSE. In this paper we describe scalability and reliability of CSE and their evaluations.

We consider a new architecture for a WSI (Wafer Scale Integration) oriented FFT processor. A two dimensional systolic array and a parallel FFT algorithm are proposed. The most significant problems are communications, reconfiguration and integrity. Considerations for those problems on WSI are presented. Our new algorithm enables computations of the FFT in parallel in any stage without multidimensional interconnections. Expected performance of the proposed architecture is also discussed.