This article presents multiwire phase encoding (MWPE), a transition signaling technique aimed at chip-to-chip communication on silicon interposer technology, where multiple, relatively low-bandwidth transmission lines can be easily routed between high-performance dies. The encoding exploits timing correlation between transitions on multiple band-limited wires to achieve high ensemble bandwidth, potentially exceeding that of parallel conventionally encoded NRZ links. The unambiguous encoding enables instantaneous bit synchronization, resulting in low-power, low-latency, PLL-/DLL-free on-chip data movement. Theoretical and practical bandwidths achievable by phase-encoded links are evaluated as a function of channel properties. Link timing, driver, and receiver circuits are implemented to evaluate the link performance and power costs associated with moving MWPE data. The Hspice simulation-based estimates indicate that a 2-mm-long MWPE link can achieve 126-Gb/s bandwidth on a lossy, dispersive transmission line medium, with an energy cost of 0.24 pJ/bit in 22-nm FDX technology.

Collective pulse oscillators (CPOs) are novel designs constructed using pulse regenerative amplifiers that exhibit time-variant gate delay based on the residual charge from past state. This property makes it possible to achieve precise phase resolutions smaller than a pulse gate delay and/or provide identical phase taps at multiple physical locations. CPOs exhibit temporal phase error correction that results in an improvement in frequency stability ∝ -10 log p for power ∝ p across all timescales beyond the correction settling time. While CPOs result in device noise-based figure of merits (FoMs) comparable to that of ring oscillators, they are more resilient to power-coupled and impulse noise. This article presents a systematic time-domain analysis of the properties of CPOs based on an abstract model that captures the time-variant delay of pulse gates. Closedform analytic solutions for CPOs disturbed by impulse noise are derived, and higher order CPOs with continuous noise injection are analyzed using behavioral simulations and characterized using Allan deviation. Hspice simulation results are presented to validate the model and compare CPOs with ring oscillators. Allan deviation and phase noise measurements on CPOs of 8 and 40 gates fabricated in GFUS8RF (130-nm) technology corroborate the theory and simulation results.

We present a design solution that allows design of higher-than-core rate operation with techniques that avoid PLL/DLL blocks to provide higher speed timing. Many modern integrated circuits (ICs) have high speed interfaces which operate at higher cycle rates than the core of the IC. As a result of the higher-than-core rate, these interfaces are not directly representable in the core sequential logic. Asynchronous pulse logic offers an alternative design method for high speed interfaces with similar performance, simpler circuitry and without resorting to high-power logic cells such as emitter coupled logic. Formal and practical considerations for constructing high-speed interfaces are described. Gate designs and timing information for example cases are presented. These cases suggest that 80% improvements on rate compared traditional clocked logic are possible.

This paper presents a practical method for improving timing uncertainty due to thermal noise in a ring oscillator. The methodology utilizes delay elements with non-linear behavior dependent on event separation, the period between successive events. Pulse logic gates are shown to have delay-separation dynamics which can impact the statistics of subsequent events in the oscillators. The slope of the delay-separation is shown to linearly improve the uncertainty in these oscillators. Multiple pulses in a ring is also shown to linearly improve the timing uncertainty.

We present a metric for event detection, targeted for the analysis of CMOS asynchronous serial data links. Our metric is used to analyze signaling strategies that allow for coincident or nearly coincident detection of both data and event timing. The metric predicts that the CMOS link signaling mechanism has substantial implicit dispersion and inter-symbol interference [ISI] tolerance when compared to conventionally timed links. In fact, it predicts correct link operation in situations where eye-diagram techniques predict link failure. Practical operation margins and metrics are described and evaluated for PCB and cabling solutions suggesting 10+ Gb/s low-power asynchronous links could be implemented in CMOS 130nm technology.

A fast technique for proving steady-state analog circuit operation constraints is described. Based on SAT, the technique is applicable to practical circuit design and modeling scenarios as it does not require algebraic device models. Despite the complexity of representing accurate transistor I/V characteristics, run-time and problem scaling behavior is excellent.

We present a framework for automated Medium Access Control (MAC) protocol generation based on a model that incorporates multiple MAC neighborhoods as well as acknowledgments. Both the advertisement and acknowledgment packets are automatically generated by an optimization program that is built based on symbolic Monte Carlo simulation. The design flow chain produces an optimal MAC protocol with respect to any desired objective function. The simulation results show that RTS/CTS control packets are automatically generated as the topology changes from single neighborhood to multi-neighborhood, and display fast convergence to the optimal solution within very reasonable computational time. This approach has the potential to change the way that MAC protocols are designed from "hand-designed protocols" to protocols designed via design automation chains.

We describe a methodology that incorporates the impact of control information transfer into MAC protocol optimization. We apply this methodology to the problem of a synchronous broadcast MAC channel, to generate the optimal protocol when the objective function is the average network throughput per slot. We describe a recursive procedure for the symbolic generation of the optimization program for any choice of the objective function. We demonstrate that this methodology produces the Random Access Channel and protocols with control information as special cases in the regimes where they are optimal. We examine the scaling of optimal throughput and of computational complexity as a function of the number of nodes and the control lifetime.

MEMOCODE Design Contest challenged teams to implement the architecture for a unique type of Deep Packet Inspector called CANSCID. This paper describes this unique problem statement, and the motivation for choosing it. This paper is followed by short descriptions prepared by individual teams detailing their particular approach to solving the problem.

The 2009 MEMOCODE Co-Design Contest is the third in the series of annual design contests organized by the MEMOCODE Conference. Contestants have one month to create the best performing design solution to a posted design challenge. The contest is open to all interested participants, and the contest rules are designed to not exclude or favor any one design methodology or platform. The goal of the contest is to invite developers of tools and platforms to showcase their technology in a leveled competition and to encourage hands-on design activities in the fields of interest of the MEMOCODE Conference. Please see http://www.memocode-conference.com for current information about this contest.

This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behavioral correctness from design performance by allowing any sub-component to dynamically stall without changing correct system activity. This is accomplished by imposition of global invariants and use of local control in the form of Synchronous-Elastic Flow (SELF) networks, which are directly synthesized. This design description format reduces the complexity of implementing correct SELF networks and does not require pre-design of a correct conventional synchronous design. The design description is a specialized guarded atomic action language which is particularly suited for succinctly describing SELF designs. We present the language syntax, semantics and synthesis techniques illustrated by the design of a latency tolerant cache controller.

This paper describes shape-preserving pulse-mode CMOS circuits for use in on-chip serial communication links. These links are competitive with conventional high-speed serial links but are simpler, more robust, and have remarkably small design overhead. In particular, they can be fabricated with limited voltage swings on minimum and medium wire sizes in highly scaled technologies as efficient point to point links. The key idea in this design is the notion of an ‘atomic’ pulse whose width and minimum period are preserved by circuit behavior, removing the jitter/length trade-offs of conventional techniques. Pulse-based data encoding removes the need for clock recovery or timing maintenance for time-scales larger than a single pulse. This allows quiescent link operation with no preamble, keep-alive, or channel encoding requirements. A prototype link design is developed and evaluated and is shown to be competitive for power, performance, and signalling robustness.

Modern embedded system designers face challenges of unprecedented scales, creating systems that integrate functionality spanning disparate scientific domains, with increasing computation demands and ever-stricter power requirements. Meeting the constraints of these systems requires practical design flows that reduce development time without sacrificing design efficiency. Novel design description methodologies coupled with automated and semi-automated synthesis paths greatly accelerate the design of modern hardware systems. In the software space, however, synthesis methods are far from producing co-designs with the necessary efficiency. This is particularly evident at the hardware/software boundary, where the tight coupling of low-level firmware routines and hardware protocols require designers to have deep design knowledge in both domains. To address this issue, we propose a latency-insensitive software execution model that allows direct connection to elastic hardware control topologies.

Micro-Electro-Mechanical Systems (MEMS) combine lithographically formed mechanical structures with electrical elements to create physical systems that operate on the scale of microns. However, the physical scale of MEMS devices can make controlling them computationally challenging because the time constants involved are often several orders of magnitude faster than macro-scale devices and because they often require very low power operation. In this paper we begin an examination of the suitability of two different digital signal processors to the high-speed closed loop control problems faced by this new and growing domain. Working with domain experts in the area we characterize the classic tight feedback control loops required by these next generation MEMS devices, we explore the sources of overhead when using existing programmable systems, and we compare these approaches to an application-specific approach of our own design. In the end we demonstrate that this nature of this problem, both in terms of the required performance and the nature of the working datasize, results in a significant gap that could perhaps be filled by more programmable designs carefully crafted to this domain.

New to the 2007 MEMOCODE conference is the HW/SW Co-Design Contest. Members of the technical and steering committees from MEMOCODE 2006 thought that the co-design practice is distinct from conventional hardware or software design practice. A co-design contest was conceived to help elucidate these issues and to foster greater interest in the design aspects of the MEMOCODE conference. The contest would also serve to showcase advances in co-design tools and methodologies. Below, we describe briefly the development of the contest format and the thinking behind the choices. The actual call-for-participation that appeared on the contest website (http://memocode07.ece.cmu.edu/contest.html) is reproduced in the appendix section.

Architectural advances of modern systems has often been at odds with control complexity, requiring significant effort in both design and verification. This is particularly true for sequential controllers, where machine complexity can quickly surpass designer ability. Traditional solutions to this problem require elaborate specifications that are difficult to maintain and extend. Further, the logic generated from these specifications bares no resemblance to the intended behavior and often fails to meet design performance constraints. In the process of designing a multi-threaded, dynamically-pipelined microcontroller, we encountered a number of common difficulties that arise from the inadequacies of traditional pipeline design methodologies. Through the use of a novel nondeterministic finite automata (NFA) specification model, we were able to implement an extensible control structure with minimal design effort. In this paper we present a viable pipeline controller specification methodology using the pyPBS language, which enables minimal effort control partitioning and compact behavioral representation. The structure of the language encourages design decisions that promote efficient modular constructions which can be easily integrated and extended. We present an overview of the our methodology including background on the pyPBS synthesis model, an architectural overview of our multi-threaded microcontroller, and implementation details for the control structure of the design including the complete control specifications. In addition, we show that the applicative nature of the pyPBS language allows for addition of a multi-cycle multiplication unit with minimal effort.

The continuing miniaturization of technology coupled with wireless networks has made it feasible to physically embed sensor network systems into the environment. Sensor net processors are tasked with the job of handling a disparate set of interrupt driven activity, from networks to timers to the sensors themselves.In this paper,we demonstrate the advantages of a tiny multi-threaded microcontroller design which targets embedded applications that need to respond to events at high speed. While multi-threading is typically used to improve resource utilization, in the embedded space it can provide zero-cycle context switching and interrupt service threads (IST), enabling complex programmable control in latency constrained environments. To explore the advantages of multi-threading on these embedded problems, we have implemented in hardware a family of controllers supporting eight dynamically interleaved threads and executing the AVR instruction set. This allows us to carefully quantify the effects of threading on interrupt latency, code size, overall processor throughput, cycle time, and design area for complete designs with different numbers of threads.

High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the final circuit layout. In this paper, we present a physically aware design flow for mapping high level application specifications to a synthesizable register transfer level hardware description. We study the problem of optimizing the data communication of the variables in the application specification. Our algorithm uses floorplan information that guides the optimization. We develop a simple, yet effective, incremental floorplanner to handle the perturbations caused by the data communication optimization. We show that the proposed techniques can reduce the wirelength of the final design, while maintaining a legal floorplan with the same area as the initial floorplan.

We present an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). We use the RTL circuit structure by extending concepts from classic automatic test-pattern generation (ATPG) algorithms and interval-arithmetic to guide the search process. We extend the idea of Boolean recursive learning on predicate logic in the RTL using Boolean and interval constraint propagation in the control and data-path of the circuit. This is used as a pre-processing step to derive relations between predicate logic signals that are used to augment the search. We demonstrate experimentally that these methods provide significant improvement over current techniques on sample benchmarks.

Rectangular cells can be flipped in place along either horizontal or vertical axis without changing the area of a layout. During floorplanning, both the location and orientation of cells are determined. However, the complexity of the floorplanning process usually means that the wirelength is not minimum. This paper proposes a technique for wirelength minimization based on in-place flipping of cells that can be applied to any floorplan style consisting of rectangular blocks or sub-blocks. Instead of conventional search procedures, a Boolean symbolic approach is proposed to generate flip-optimal floorplans. Experimental results show that it can effectively reduce the wirelength of current state of the art approaches, at no cost in area and with modest runtimes.

We present a method that combines interval-arithmetic (IA) and Boolean reasoning with structural hashing for simplifying SAT problems on circuits expressed at the register-transfer level. We demonstrate that simple transformations based on interval-arithmetic operations can significantly reduce the complexity of the problem. We identify cases where the inherent over-approximations in IA operations can be reduced. We demonstrate that these techniques can significantly reduce RTL-SAT instances in size and runtime.

This paper describes a practical technique for the optimal scheduling of control dominated systems minimizing the weighted average latency over all control branches. Such a weighted metric is crucial for control dependent scheduling to accommodate practical architectural goals. In contrast to most weighting mechanisms, a nonBayesian probabilistic measure is used to avoid assumptions of branch independence. The underlying scheduling model allows general FSM-based models for operations, captures several forms of speculative execution and scales well with increasing control complexity.

This paper presents results on processor specification from a specialized high-level finite state machine (FSM) language. The language is an extension and enhancement of earlier production based specification (regular automata) work using modern software techniques of modularization, abstraction, and object orientation. A brief overview of the language, its synthesis technique, description methods and advantages are presented for a variety of common synchronous pipeline structures in the context of the design of a synthesizable instruction-stream parallel microcontroller.

Variations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise-on-signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics. The expressions can be used in any existing circuit performance optimization design flow or can be combined into any delay calculations as a correction factor.

Variation of power and ground levels affect VLSI circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise on signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply level-induced jitter characteristics.

We describe a set of techniques for representing the high-level behavior of a digital subsystem as a collection of nondeterministic finite automata, NFA. Desired behavioral dynamics such as functional dependencies, sequential timing, and sequencing, and control state are similarly modeled. Using techniques similar to that used in formal model checking, we implicitly explore the possible execution sequences of the system, obeying all imposed constraints. This provides a very general, systematic mechanism for performing high-level synthesis of cyclic, control dominated behaviors, constrained by arbitrary sequential constraints. In this paper, we show that these techniques are scalable to practical problem sizes and complexities by constructing a high-level model of a (MIPS IV) RISC microprocessor and then performing exact scheduling and related design tradeoffs on this model. The model is constructed at the level of register transactions to address the majority of contention and arbitration issues of architectural interest.

This paper presents an exact technique for scheduling looping data-flow graphs that implicitly supports functional pipelining and loop winding. Automata-based symbolic modeling provides efficient representation of all causal executions of a given behavioral description subject to finite state bounds. Since a complete set of scheduling solutions is found, further incremental refinements, such as sequential interface protocol constraints, can be easily accommodated. Efficiency In the implementation Is maintained by careful formulation of the automata and by judicious exploration techniques. Results are presented for traditionally referenced benchmarks, several large synthetic benchmarks, and a practical industrial example.

This paper presents a very general, exact technique for scheduling looping data-flow graphs. In contrast to the conventional technique using loop iteration variables and integer linear programming, the new technique uses implicit symbolic automata techniques to represent the problem instance. The new technique has several advantages, such as incremental refinement, efficient variable usage and ability to accommodate practical design constraints. A small case study demonstrates the flexibility and viability of this technique.

In this paper, we present a practical method for verifying the functional equivalence of two synchronous sequential designs. This tool is based on our earlier framework that uses Automatic Test Pattern Generation (ATPG) techniques for verification. By exploring the structural similarity between the two designs under verification, the complexity can be reduced substantially. We enhance our framework by three innovative features. First, we develop a local BDD-based technique which constructs Binary Decision Diagram (BDD) in terms of some internal signals, for identifying equivalent signal pairs. Second, we incorporate a technique called partial justification to explore not only combinational similarity, but also sequential similarity. This is particularly important when the two designs have a different number of flip-flops. Third, we extend our gate-to-gate equivalence checker for RTL-to-gate verification. Two major issues are considered in this extension: (1) how to model and utilize the external don't care information for verification; and (2) how to extract a subset of unreachable states to speed up the verification process. Compared with existing approaches based on symbolic Finite State Machine (FSM) traversal techniques, our approach is less vulnerable to the memory explosion problem and, therefore, is more suitable for a lot of real-life designs. Experimental results of verifying designs with hundreds of flip-flops will be presented to demonstrate the effectiveness of this approach.

This paper presents a technique for highly constrained event sequence scheduling. System resource protocols as well as an external interface protocol are described by non-deterministic finite automata (NFA). All valid schedules which adhere to interfacing constraints and resource bounds for flow graph described behavior are determined exactly. A model and scheduling results are presented for an extensive design example.

This paper presents an efficient encoding and automaton construction which improves performance of automata-based scheduling techniques. The encoding preserves knowledge of what operations occurred previously but excludes when they occurred, allowing greater sharing among scheduling traces. The technique inherits all of the features of BDD-based control dominated scheduling including systematic speculation. Without conventional pruning, all schedules for several large samples are quickly constructed.

Generalizes ALAP (as late as possible) bounds for the exact scheduling problem on a pre-defined data path. Conventional bounds are inapplicable because of the possible requirement of re-computing operands for minimal schedule length. Efficient techniques are presented for constructing the new bounds which are sensitive to point-to-point delays via transitive memory units. An efficient operand mapping bound is also described. Based on these two bounds, time improvement factors of 50 have demonstrated in exact scheduling results.

Conventional High-level Synthesis techniques create an interconnection structure before physical design. Following physical design, connection delays and special requirements may cause the structure to fail timing or performance constraints. Alterations to this structure are often limited since it was created either after or during the binding and scheduling tasks. In this paper we present a set of techniques which analyze the timing trade-offs associated with the position-specific interconnection network given the freedom of high-level binding and rescheduling changes. 3. Problem Specification In this work, the automata based data-path model introduced in [7] is utilized to implicitly execute a series of data flows on a detailed RTL data path. Given the additions of a floorplan, a set of alternative interconnection networks, and a set of timing ranges, the automata will produce a timed output sequence as well as characterize the timing behavior of the "care paths" for each element ...

Implementation of an Efficient Parallel BDD Package by Anthony L. Stornetta Large BDD applications are generally limited by a processor's resources, especially physical memory. In large BDD applications, virtual memory is not an attractive solution for conventional depth-first BDD algorithms. Irregular memory access patterns in the algorithm cause thrashing, which severely impairs performance. One solution to overcoming this resource limitation is to utilize the memory of multiple networked workstations. A number of different forms of parallelism can be exploited in depth-first algorithms performed on a distributed BDD. The BDD structure is stored in a distributed hash table and can be accessed simultaneously by multiple processors. An unlimited number of multiple BDD operations may be concurrently issued. In essence, the package can simultaneously execute multiple threads of computation on a distributed BDD. This thesis presents an efficient parallel BDD package for a distributed en...

High speed synchronous digital systems require large switching currents to facilitate rapid signal transitions. These large currents create voltage drops on the power distribution network and necessitate expensive chip packaging with a large number of supply pins. In this paper we propose a novel technique to reduce the dynamic transient current drawn from the supply pins. Our approach is based on sub-dividing the synchronous clocking into multiple sub-clocks with relative skew. This spreads the computation across the entire clock cycle instead of largely occurring at the beginning. Timing constraints must also be obeyed, so that no races or timing errors are introduced. We propose an exact algorithm based on integer linear programming to solve this problem. We have used our method in the design of a 5 GHz ECL encoder chip to achieve a factor of two reduction in ground bounce, as shown by HSPICE simulations. We also obtained order-of-magnitude improvements in ground bounce on benchmarks laid our in submicron CMOS technology. The approach potentially leads to significant reductions in packaging costs.

This paper describes an exact symbolic formulation of control-dependent, resource-constrained scheduling. The technique provides a closed-form solution set in which all satisfying schedules are encapsulated in a compressed OBDD-based representation. This solution format greatly increases the flexibility of the synthesis task by enabling incremental incorporation of additional constraints and by supporting solution space exploration without the need for rescheduling. The technique provides a systematic treatment of speculative operation execution in arbitrary forward-branching control/data paths. An iterative construction method is presented along with benchmark results. The experiments demonstrate the ability of the proposed technique to efficiently exploit parallelism not explicitly specified in the input description.

We present an automata model which concisely captures the constraints imposed by a data-path, such as bus hazards, register constraints, and control encoding limitations.A set of uniform base components for depicting general data-paths and techniques for systematic translation of such depictions into Boolean functions are described.Finally, this model is expanded to represent the limitations of generating as well as moving operands by incorporating data-flow graphs.The benefits of this representation are demonstrated by modeling a commercial DSP microprocessor.

We present a data-path model which concisely captures the path constraints imposed by a data-path, such as bus hazards, register constraints, and control encoding limitations. A process for expressing arbitrary datapaths in terms of this model's base components and techniques for systematic translation into Boolean functions are described. Finally, this model is expanded to represent the limitations of generating as well as moving operands by incorporating dataflow graphs. The power of this representation is demonstrated by applying the path-constrained model to scheduling on a commercial DSP microprocessor.

Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximization of throughput is desired. In this paper, an exact and efficient conditional resource sharing analysis using a guardbased control representation is presented. The analysis is transparent to a scheduler implementation. The proposed technique systematically handles complex conditional resource sharing for cases when folded (software pipelined) loops include conditional behavior within the loop body.

This paper describes a symbolic formulation that allows incorporation of speculative operation execution (preexecution) in an exact control-dependent scheduling of arbitrary forward branching control/data paths.The technique provides a closed form solution set in which all satisfying schedules are encapsulated in a compressed OBDD-based representation.To extract parallelism implicit in the input specification Boolean 'guard' functions are used to identify paths where operations have to be scheduled and the execution order of the conditionals is dynamically resolved.An efficient and systematic iterative construction method is presented along with benchmark results.

This paper describes a new high-level synthesis system based on the hierarchical production based specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables, and that the designer does not describe a particular form of implementation. The production-based specification also separates the specification of the control aspects and data-flow aspects of the design. The control is implicitly described via the production hierarchy, while the data-flow is described as action computations. This approach is a hardware analog of popular software engineering techniques. The Clairvoyant system automatically constructs a controlling machine from the PBS and this process is not impacted by the possibly exponentially larger deterministic state space of the designs. The encodings generated by the constructions compare favorably to encodings derived using graph-based state encoding techniques in terms of logic complexity and logic depth. These construction techniques utilize recent advances in BDD techniques.>

Article High-level symbolic construction technique for high performance sequential synthesis Share on Authors: Andrew Seawright View Profile , Forrest Brewer View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 424–428https://doi.org/10.1145/157485.164961Online:01 July 1993Publication History 15citation193DownloadsMetricsTotal Citations15Total Downloads193Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The authors propose a novel specification for tightly constrained processing elements based on recognizing concurrent sequences of data flow. This specification has several benefits, notably it allows a very concise representation of complex internal semantics and interface protocols. Particular advantages exist with specifying timing constraints and performance cost functions for control dominated applications. The specification can be made canonical and leads to an interesting formulation of the scheduling problem.>

The authors present a novel decomposition of the high-level data-path synthesis problem taking as input scheduled procedural behavior and outputting geometrically placed and optimized linear data-paths. The technique uses communication based analysis to allow simultaneous synthesis of the placement, bindings, and RTL topology for high performance linear data-paths. In effect, the procedure creates an architecture and a layout with specified performance and cost constraints.>

This paper addresses relevant issues in connectivity synthesis particularly with respect to other design concerns in high-level behavioral synthesis.A restricted model is used to run a series of design experimerus to provide insight into the relationship between scheduling, conrwctivity, and placement & routing.Contrary to the common approach of counting multiplexer, multiplexer inputs, and busses, this approach looks at more germanz issues, namely: I) How to decide how much a "bus" is really going to cost, 2) How much does "load balanced" scheduling help, especially in the case of resource constrained scheduling, and 3) Should the number of multiplexer inputs really be the main criterion for judging the connectivity quality of the designs?

This paper applies a form of instruction stream interleaving to the problem of high performance real-time systems.Such systems are characterized by high bandwidth, stochastically occurring interrupts as well as high throughput requirements,The DISC computer is based on dynamic interleaving where the next instruction to be executed is dynamically selected from several possible simultaneously active streams.Each stream context is stored internally making possible active task switching in a single instruction cycle.For several RTS applications the DISC concept promises higher computation throughput at lower cost than is possible on contemporary RISC processors.Implementation and register organization details are presented as well as simulation results.

The Chippe system for constrained behavioural architecture synthesis uses a novel closed-loop design iteration technique in which the present state of the design is analyzed with respect to the goals and then modified for the next iteration. In this way the design state is iteratively driven towards meeting the global constraints imposed by the designer. The design synthesis is performed by a set of algorithmic tools specially constructed to permit the imposition of a wide variety of local constraints, and by a rule-based system which makes design analysis and modification decisions to set these local constraints. Key to these decisions is a design evaluator which examines the present state of the design and interactively reports its findings to the rule-based system. The closed-loop iteration strategy, the interaction between the rule base and the tools, and the evaluation performed to support the design decisions are detailed. Also presented are results from sample designs, including designs for the TMS320 digital signal processor chip.>

This paper describes the principles and implementation of design-process control in a micro-architecture compiler. The knowledge-base relies on both local and global evaluations to determine strategies to achieve global goals and then implements those strategies by manipulating hardware allocations and search heuristics. A system overview and annotated sample run are presented.

Article Free Access Share on An expert-system paradigm for design Authors: Forrest D. Brewer Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1304 West Springfield Ave., Urbana, Illinois Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1304 West Springfield Ave., Urbana, IllinoisView Profile , Daniel D. Gajski Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1304 West Springfield Ave., Urbana, Illinois Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1304 West Springfield Ave., Urbana, IllinoisView Profile Authors Info & Claims DAC '86: Proceedings of the 23rd ACM/IEEE Design Automation ConferenceJuly 1986 Pages 62–68Published:02 July 1986Publication History 10citation250DownloadsMetricsTotal Citations10Total Downloads250Last 12 Months4Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF