A Pseudo Random Number Generator (PRNG) produces a sequence whose randomness is evaluated by statistical tests like NIST and TestU01. The random sequences are deterministic and reproducible when using the same seed value. In this manner, and for cryptographic applications, the key size of a PRNG must be increased to resist brute force attacks. Henceforth, a fractional-order chaotic system, like the Lorenz one, is suitable to be used to design a PRNG, which implementation can be performed by using embedded devices such as the low-cost EPS32 (32-bit LX6 microprocessor) and field-programmable gate array (FPGA). To increase the throughput, the fractional Lorenz system is integrated with an approximated two steps Runge–Kutta method. An analysis in performed to find the domain of attraction for each state variable, and to verify that the PRNG produces non-correlated sequences. The hardware implementation is detailed by establishing the number of bits (or keys) required for the PRNG to guarantee its suitability for cryptographic applications. Finally, the hardware design of a PRNG using the fractional Lorenz system provides a throughput of 4.99 Mbits/sec in the EPS32 platform, and 112.96 Mbits/sec in the FPGA.

In this article, we propose a novel approach to detect the occupancy behavior of a building through the temperature and/or possible heat source information. The new method can be used for energy reduction and security monitoring for emerging smart buildings. Our work is based on a building simulation program, EnergyPlus, from the Department of Energy. EnergyPlus can model various time-series inputs to a building such as ambient temperature; heating, ventilation, and air-conditioning (HVAC) inputs; power consumption of electronic equipment; lighting; and number of occupants in a room, sampled each hour, and produce resulting temperature traces of zones (rooms). Two machine-learning-based approaches for detecting human occupancy of a smart building are applied herein, namely support vector regression (SVR) and recurrent neural network (RNN). Experimental results with SVR show that the four-feature model provides accurate detection rates, giving a 0.638 average error and 5.32% error rate, and the five-feature model delivers a 0.317 average error and 2.64% error rate. This indicates that SVR is a viable option for occupancy detection. In the RNN method, Elman’s RNN can estimate occupancy information of each room of a building with high accuracy. It has local feedback in each layer and, for a five-zone building, it is very accurate for occupancy behavior estimation. The error level, in terms of number of people, can be as low as 0.0056 on average and 0.288 at maximum, considering ambient, room temperatures, and HVAC powers as detectable information. Without knowing HVAC powers, the estimation error can still be 0.044 on average, and only 0.71% estimated points have errors greater than 0.5. Our article further shows that both methods deliver similar accuracy in the occupancy detection. But the SVR model is more stable for adding or removing features of the system, while the RNN method can deliver more accuracy when the features used in the model do not change a lot.

Three methods for extracting the behavioral modeling coefficients of the memory polynomial model are compared herein. The first one is the ordinary least square regression, which is widely used for adjusting model parameters; the second is the order recursive least squares, which is suitable for exploring the optimal nonlinearity order and memory depth by comparing subsequent errors while increasing the complexity of the model; and the third is called sequential least square, which is very attractive to be implemented and it only requires identifying the behavior of a power amplifier, and calculating the most accurate model coefficients for each measurement. The equations of the three methods were simulated in Matlab for the NXP 10W power amplifier with complex baseband data, and their implementation was evaluated with normalized mean square error. Also a comparison of their computational complexity based on Halstead metrics is given herein.

It is well known that Pareto based algorithms do not scale when the number of objectives is greater than three. That way, it is an open problem in integrated circuit design because optimizing amplifiers by multi-objective evolutionary algorithms requires evaluating many objectives with many constraints. In this manner, we show the usefulness of MOMBI, an algorithm based on R2 indicator, for improving the optimal sizing of amplifiers designed with MOSFETs. It is highlighted that such kind of algorithms could lead to solve problems in analog integrated circuit optimization when considering many objectives. In addition, a handling constraint scheme is incorporated to MOMBI. The optimization algorithm based on R2 indicator is applied herein to an amplifier that is used to implement a universal active filter showing good SPICE simulations results.

An strategy based on the optimal computing budget allocation (OCBA) approach is presented to reduce the simulation cost in the yield optimization of analog integrated circuits (ICs), when it is performed on classical Monte Carlo simulations. OCBA is applied to distribute the large portion of the budget simulations among critical IC sizing optimization cases, while limiting the simulations for the non-critical cases. The optimal sizing is performed by applying three evolutionary algorithms, namely: non-dominated sorting genetic algorithm (NSGA-II), multi-objective evolutionary algorithm with decomposition (MOEA/D), and particle swarm optimization (PSO). They are executed within the OCBA-based strategy to enhance the yield of an operational transconductance amplifier using IC technology of 90 nm.

Yield estimation for analog integrated circuits are crucial for analog circuit design and optimization in the presence of process variations. In this paper, we present a novel analog yield estimation method based on performance bound analysis technique in frequency domain. The new method first derives the transfer functions of linear (or linearized) analog circuits via a graph-based symbolic analysis method. Then frequency response bounds of the transfer functions in terms of magnitude and phase are obtained by a nonlinear constrained optimization technique. To predict yield rate, bound information are employed to calculate Gaussian distribution functions. Experimental results show that the new method can achieve similar accuracy while delivers 20 times speedup over Monte Carlo simulation of HSPICE on some typical analog circuits.

A multi-parameter sensitivity approach based on Richardson extrapolation, and applied to the optimal sizing of analog integrated circuits (ICs), is presented. First, the multiobjective evolutionary algorithm (EA) called non-dominated sorting genetic algorithm (NSGA-II), is applied to compute the feasible sizes of analog ICs, i.e. the optimal width and length (W/L) of every metal-oxide-semiconductor field-effect-transistor (MOSFET) is found. At this stage, the simulation program with integrated circuits emphasis (SPICE) is used to evaluate the electrical characteristics of analog ICs. Second, the multiparameter sensitivity analysis based on Richardson extrapolation, is applied to approximate the partial derivatives associated to the sensitivities on the performances of the ICs with respect to W/L of every MOSFET. The cases of study are three analog ICs, namely: voltage follower (VF), positive-type second generation current conveyor (CCII+), and current-feedback operational amplifier (CFOA). The proposed approach selects W/L feasible sizes presenting the lower sensitivities that are computed from the corresponding Pareto sets. Finally, 18 feasible (W/L sizes) solutions accomplishing 18 performance objectives and guaranteeing low W/L sensitivities for a complementary metal-oxide-semiconductor (CMOS) CFOA, are listed in Table I.

This investigation shows the modeling and simulation of the synchronization of two multi-scroll chaotic oscillators in a master-slave topology. The synchronization is performed by Generalized Hamiltonian forms and observer approach from nonlinear control theory. The case of study consists of two 4-scroll attractors based on saturated function series. Finally, the numerical simulation of the synchronization, from the mathematical description, and the circuit implementation using HSPICE models of opamps, show the good agreement between theory and experiment results.

In this article, we propose a new performance bound analysis of analog circuits considering process variations. We model the variations of component values as intervals measured from tested chips and manufacture processes. The new method first applies a graph-based analysis approach to generate the symbolic transfer function of a linear(ized) analog circuit. Then the frequency response bounds (maximum and minimum) are obtained by performing nonlinear constrained optimization in which magnitude or phase of the transfer function is the objective function to be optimized subject to the ranges of process variational parameters. The response bounds given by the optimization-based method are very accurate and do not have the over-conservativeness issues of existing methods. Based on the frequency-domain bounds, we further develop a method to calculate the time-domain response bounds for any arbitrary input stimulus. Experimental results from several analog benchmark circuits show that the proposed method gives the correct bounds verified by Monte Carlo analysis while it delivers one order of magnitude speedup over Monte Carlo for both frequency-domain and time-domain bound analyses. We also show analog circuit yield analysis as an application of the frequency-domain variational bound analysis.

The shrinking technology feature size and dense large-scale integration make process variation a challenging issue directly confronting the latest design automation tools. Process variation causes severe variation in interconnect networks, including very large-scale integrated interconnect structures, such as clock trees, clock mesh, power-ground networks, and other wiring structures in 3-D integrated circuits. The traditional moment computation techniques are only partly useful for analyzing such variational problems, however, their computational efficiency cannot meet the quickly rising needs, such as statistical analysis. This paper presents a novel symbolic moment calculator (SMC) for variational interconnect analysis. The moment calculator is constructed in a regular data structure that incorporates binary decision diagrams for data storage and computation. Given an interconnect circuit, such a computation diagram has to be constructed only once and can be repeatedly invoked for computation of moments with varying parameter values. Also, the SMC is friendly to interconnect synthesis in that it can be incrementally modified according to the modifications made to the circuit structure. Applications of the SMC for fast moment computation, sensitivity analysis, and statistical timing analysis are addressed. Significant efficiency is demonstrated comparing to other existing methods.

A trade-off analysis on the number of scrolls and the operating frequency is presented. To do so, nonlinear system parameters, real physical active device parameters and the operating frequency are taken into account to model the behavior of the saturated nonlinear function series approximated by a piecewise-linear description. As a consequence, not only the trade-off between the number of scrolls and the operating frequency is investigated, which depends directly on the behavior at the operating frequency of the nonlinear function, but also chaotic attractors are efficiently synthesized without the application of scaling techniques. Theoretical calculations are in good agreement with numerical simulations and a prediction on the maximum number of scrolls that can be synthesized for a particular frequency is also given.

A novel extended method to approximate the behavioral model of current-mode analog circuits (CMACs) is presented. The nullor is employed to model the behavior of a MOS transistor (MOST) together with its parasitic elements. In a first part, the signal-path (SP) into a CMAC is approached by using the nullor properties. In the second part, the behavioral model associated to each MOST is generated and it is more simple in comparison with the original model. As a consequence, in the third part, an admittance matrix of reduced size is built and used to compute small-signal characteristics of CMACs, where the order is given by the number of SP-nodes minus the number of nullors. The proposed technique is illustrated by computing the fully-symbolic transfer function of a positive second generation current conveyor (CCII+) and compared with Hspice simulation.