We present a new approach to the automatic layout design for VLSI chips which incorporates timing information to influence the placement and wiring processes. This approach is an extension of the hierarchical layout method, in which placement and wiring are performed simultaneously [1]. We add a third phase of timing to the hierarchy, without affecting the computational complexity of the basic algorithm.

We propose a new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels. Popularity of gate arrays technologies still remains high among VLSI chip manufacturers and, as the scale of integration grows, the interconnection problem becomes increasingly difficult if not intractable. The same is true for problems of switchbox and channel routing, which usually arise in custom designs; the uniformity of wiring substrate unites them with gate array routing problem. Our approach was initially aimed at gate arrays, but it extends naturally to switchboxes and channels. Uniformity of the wiring substrate is the crucial assumption of the method. It assumes that horizontal and vertical wire segments are realized on different wiring layers and vias are introduced each time a wire changes direction. Any "jogs" ("wrong way" wires) are prohibited. Within these limitations our approach is advantageous over the existing wiring methodologies. Our final layout of wires is independent of both net ordering and ordering of pins within the nets. The wire densities we are able to achieve are often higher than those achieved by other routers. Because of the hierarchical nature of our method it is inherently fast, usually by an order of magnitude faster than the routers based on wave propagation (maze running) technique.