As part of the design of large integrated circuits, one must verify that the power delivery network provides supply and ground voltages to the circuit that are within specified ranges. We introduce the concept of time-frequency description of circuit currents using wavelets, and use that to set up an optimization framework that finds the worst-case supply/ground voltage fluctuations. This framework allows for the quick determination of the impact of either the package or the die on the worst-case behavior, which enables their codesign. This approach has been applied to an industrial microprocessor design, resulting in realistic and nonobvious worst-case waveforms.

The verification of power grids in modern integrated circuits must start, at design time, where circuit information is unknown but could be specified or inferred from design or architectural considerations. This work builds on previously proposed techniques to deal with circuit uncertainty in the framework of linear current constraints, but proposes a cost-controlled solution, by following a geometric approach, and transforming a problem that requires as many linear programs as there are power grid nodes, to another involving a user-limited number of solutions of one linear system.

As power grid safety becomes increasingly important in modern integrated circuits, so does the need to start power grid verification early in the design cycle and incorporate circuit uncertainty of the early stages into useful power grid information. This work adopts the framework of capturing circuit uncertainty via constraintson circuit currents, and follows a geometric approachto transform a problem whose solution requires as many linear programs as there are power grid nodes, to another involving a user-limited number of solutions of one linear system.

A model for process-induced parameter variations is proposed, combining die-to-die, within-die systematic, and within-die random variations. This model is put to use toward finding suitable timing margins and device file settings, to verify whether a circuit meets a desired timing yield. While this parameter model is cognizant of within-die correlations, it does not require specific variation models, layout information, or prior knowledge of intrachip covariance trends. The approach works with a "generic" critical path, leading to what is referred to as a "process-specific" statistical-timing-analysis technique that depends only on the process technology, transistor parameters, and circuit style. A key feature is that the variation model can be easily built from process data. The derived results are "full-chip," applicable with ease to circuits with millions of components. As such, this provides a way to do a statistical timing analysis without the need for detailed statistical analysis of every path in the design

The ongoing trends in technology scaling imply a reduction in the transistor threshold voltage (V/sub th/). With smaller feature lengths and smaller parameters, variability becomes increasingly important, for ignoring it may lead to chip failure and assuming worst case renders almost any design nonachievable. This paper presents a methodology for the analysis and verification of the power grid of integrated circuits considering variations in leakage currents. These variations are large due to the exponential relation between leakage current and transistor threshold voltage and appear as random background noise on the nodes of the grid. We propose a lognormal distribution to model the grid voltage drops, derive bounds on the voltage-drop variances, and develop a numerical Monte Carlo method to estimate the variance of each node voltage on the grid. This model is used toward the solution of a statistical formulation of the power-grid-verification problem.

To ensure reliable performance of a chip, design verification of the power grid is of critical importance. This paper builds on previous work that models the working behavior of the circuit in terms of abstracted current constraints and solves for worst-case voltage drop on the grid as a linear program. The main motivation is to allow the efficient verification of local power grid sections or blocks, enabling incremental design analysis of the grid. This approach substantially improves the computational time by reducing the problem size and the constraint set and replacing them by black box macromodels. This increase the capacity of the solver to handle industrial sized grids.

Transistor threshold voltages Vth have been reduced as part of on-going technology scaling. The smaller Vth values feature increased fluctuations due to process variations, with a strong within-die component. Correspondingly, given the exponential dependence of leakage on.Vth, circuit leakage currents are increasing significantly and have strong within-die statistical variations. With these currents loading the power grid, the grid develops large voltage drops, which is an unavoidable background level of noise on the grid. We develop techniques for estimation of the statistics of the leakage-induced power grid voltage drop based on given statistics of the circuit leakage currents.