Alan Gara

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13ranked-venue papers

0as first author

0since 2021 · last 2008

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 10Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems 6 papers		High-performance computing · 42% Interconnection networks and networks-on-chip · 18% Processor architecture and microarchitecture · 11%
Interdisciplinary, comprehensive, and emerging computing 1 paper		Computational science and engineering · 100%

Topics — the 12 heaviest of 16, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
High-performance computing › supercomputing bluegene/l	0.1	2	2004	Unlocking the Performance of the BlueGene/L Supercomputer · SC 2004 An overview of the BlueGene/L Supercomputer · SC 2002
High-performance computing supercomputing	0.1	2	2004	QCDOC: A 10 Teraflops Computer for Tightly-Coupled Calculations · SC 2004 An overview of the BlueGene/L Supercomputer · SC 2002
Memory systems cache coherence	0.1	1	2008	Design and implementation of the blue gene/P snoop filter · HPCA 2008
High-performance computing supercomputer architecture	0.1	2	2004	Unlocking the Performance of the BlueGene/L Supercomputer · SC 2004 QCDSP: A Teraflop Scale Massively Parallel Supercomputer · SC 1997
High-performance computing › large-scale simulation quantum chromodynamics simulation	0.1	1	2006	Gordon Bell finalists II - The BlueGene/L supercomputer and quantum ChromoDynamics · SC 2006
High-performance computing › supercomputing supercomputer performance	0.1	1	2006	Gordon Bell finalists II - The BlueGene/L supercomputer and quantum ChromoDynamics · SC 2006
Integrated circuit design › digital circuit design › arithmetic circuit design floating-point unit	0.0	1	2004	Unlocking the Performance of the BlueGene/L Supercomputer · SC 2004
Processor architecture and microarchitecture instruction set architecture	0.0	1	2004	QCDOC: A 10 Teraflops Computer for Tightly-Coupled Calculations · SC 2004
Integrated circuit design system-on-chip	0.0	1	2002	An overview of the BlueGene/L Supercomputer · SC 2002
Processor architecture and microarchitecture chip multiprocessor	0.0	1	2008	Design and implementation of the blue gene/P snoop filter · HPCA 2008
Performance modeling and evaluation benchmarking	0.0	1	2004	Unlocking the Performance of the BlueGene/L Supercomputer · SC 2004
Interconnection networks and networks-on-chip › network topology torus network	0.0	1	2004	Unlocking the Performance of the BlueGene/L Supercomputer · SC 2004

Methods — techniques the papers use, named apart from their topics

scaling analysis · 0.1simulation · 0.1performance analysis · 0.0conjugate gradient solver · 0.0benchmarking · 0.0system architecture design · 0.0performance scaling studies · 0.0custom hardware design · 0.0

Year	Publication	Venue	Position
2008	Design and implementation of the blue gene/P snoop filter abstract As multi-core processors evolve, coherence traffic between cores is becoming problematic, both in terms of performance and power. The negative effects of coherence (snoop) traffic can be significantly mitigated through snoop filtering. Shielding each cache with a device that can squash snoop requests for addresses known not to be in cache improves performance significantly for caches that cannot perform normal load and snoop lookups simultaneously. In addition, reducing snoop lookups yields power savings. This paper describes the design of the Blue Gene/P snoop filters, and presents hardware measurements to demonstrate their effectiveness. The Blue Gene/P snoop filters combine stream registers and snoop caches to capture both the locality of snoop addresses and their streaming behavior. Simulations of SPLASH-2 benchmarks illustrate tradeoffs and strengths of these two techniques. Their combination is shown to be most effective, eliminating 94-99% of all snoop requests using very few stream registers and snoop cache lines. This translates into an average performance improvement of almost 20% for the NAS benchmarks running on an actual Blue Gene/P system. Valentina Salapura, Matthias A. Blumrich, Alan Gara	HPCA	3
2008	Next-Generation Performance Counters: Towards Monitoring Over Thousand Concurrent Events abstract We present a novel performance monitor architecture, implemented in the Blue Gene/P™ supercomputer. This performance monitor supports the tracking of a large number of concurrent events by using a hybrid counter architecture. The counters have their low order data implemented in registers which are concurrently updated, while the high order counter data is maintained in a dense SRAM array that is updated from the registers on a regular basis. The per formance monitoring architecture includes support for per- event thresholding and fast event notification, using a two- phase interrupt-arming and triggering protocol. A first implementation provides 256 concurrent 64b counters which offers an up to 64x increase in counter number compared to performance monitors typically found in microprocessors today, and thereby dramatically expands the capabilities of counter-based performance tuning. Valentina Salapura, Karthik Ganesan 0006, Alan Gara, Michael Gschwind, James C. Sexton, Robert Walkup	ISPASS	3
2007	Exploiting eDRAM bandwidth with data prefetching: simulation and measurements abstract Compared to conventional SRAM, embedded DRAM (eDRAM) offers power, bandwidth and density advantages for large on-chip cache memories. However, eDRAM suffers from comparatively slower access times than conventional SRAM arrays. To hide eDRAM access latencies, the Blue Gene/L(&) supercomputer implements small private prefetch caches. We present an exploration of design trade-offs for the prefetch D-cache for eDRAM. We use full system simulation to consider operating system impact. We validate our modeling environment by comparing our simulation results to measurements on actual Blue Gene systems. Actual execution times also include any system effects not modeled in our performance simulator, and confirm the selection of simulation parameters included in the model. Our experiments show that even small prefetch caches with wide lines efficiently capture spatial locality in many applications. Our 2kB private prefetch caches reduce execution time by 10% on average, effectively hiding the latency of the eDRAM-based memory system. Valentina Salapura, José R. Brunheroto, Fernando F. Redígolo, Alan Gara	ICCD	4
2006	Gordon Bell finalists II - The BlueGene/L supercomputer and quantum ChromoDynamics abstract We describe our methods for performing quantum chromodynamics (QCD) simulations that sustain up to 20% of the peak performance on BlueGene supercomputers. We present our methods, scaling properties, and first cutting edge results relevant to QCD. We show how this enables unprecedented computational scale that brings lattice QCD to the next generation of calculations. We present our QCD simulation that achieved 12.2 Teraflops sustained performance with perfect speedup to 32K CPU cores. Among other things, these calculations are critical for cosmology, for the heavy ion experiments at RHIC-BNL, and for the upcoming experiments at CERN-Geneva. Furthermore, we demonstrate how QCD dramatically exposes memory and network latencies inherent in any computer system and propose that QCD should be used as a new, powerful HPC benchmark. Our sustained performance demonstrates the excellent properties of the BlueGene/L system. Pavlos Vranas, Gyan Bhanot, Matthias A. Blumrich, Dong Chen 0005, Alan Gara, Philip Heidelberger, Valentina Salapura, James C. Sexton	SC	5
2005	Early Experience with Scientific Applications on the Blue Gene/L Supercomputer Gheorghe Almási 0001, Gyan Bhanot, Dong Chen 0005, Maria Eleftheriou, Blake G. Fitch, Alan Gara, Robert S. Germain, John A. Gunnels, Manish Gupta 0002, Philip Heidelberger, Michael Pitman, Aleksandr Rayshubskiy, James C. Sexton, Frank Suits, Pavlos Vranas, Robert Walkup, T. J. Christopher Ward, Yuriy Zhestkov, Alessandro Curioni, Wanda Andreoni, Charles Archer, José E. Moreira, Richard Loft, Henry M. Tufo, Theron Voran, Katherine Riley	Euro-Par	6
2005	Scaling physics and material science applications on a massively parallel Blue Gene/L system abstract Blue Gene/L represents a new way to build supercomputers, using a large number of low power processors, together with multiple integrated interconnection networks. Whether real applications can scale to tens of thousands of processors (on a machine like Blue Gene/L) has been an open question. In this paper, we describe early experience with several physics and material science applications on a 32,768 node Blue Gene/L system, which was installed recently at the Lawrence Livermore National Laboratory. Our study shows some problems in the applications and in the current software implementation, but overall, excellent scaling of these applications to 32K nodes on the current Blue Gene/L system. While there is clearly room for improvement, these results represent the first proof point that MPI applications can effectively scale to over ten thousand processors. They also validate the scalability of the hardware and software architecture of Blue Gene/L. Gheorghe Almási 0001, Gyan Bhanot, Alan Gara, Manish Gupta 0002, James C. Sexton, Robert Walkup, Vasily V. Bulatov, Andrew W. Cook, Bronis R. de Supinski, James N. Glosli, Jeffrey A. Greenough, François Gygi, Alison Kubota, Steve Louis, Thomas E. Spelce, Frederick H. Streitz, Peter L. Williams, Robert K. Yates, Charles Archer, José E. Moreira, Charles A. Rendleman	ICS	3
2005	Data cache prefetching design space exploration for BlueGene/L supercomputer abstract Scientific applications exhibit good spatial and temporal data memory access locality. It is possible to hide memory latency for the level 3 cache, and reduce contention between multiple cores sharing a single level 3 cache, by using a prefetch cache to identify data streams which can be profitably prefetched, and decouple the cache line size mismatch between L3 cache and the level 1 data cache. In this work, a design space exploration is presented, which helped shape the design of the BlueGene/L supercomputer memory sub-system. The prefetch cache consists of a small number of 128 line buffers that speculatively prefetches data from the L3 cache, since applications present some sequential access pattern, this prefetching scheme increases the likelihood that a request from the level 1 data cache was present in the prefetch cache. Since most compute intensive applications contain a small number of data streams, it is sufficient for the prefetch cache to have small number of line buffers to track and detect the data streams. This paper focuses on the evaluation of stream detection mechanisms and the influence of varying the replacement policies for stream prefetch caches. José R. Brunheroto, Valentina Salapura, Fernando F. Redígolo, Dirk Hoenicke, Alan Gara	SBAC-PAD	5
2004	The eDRAM based L3-Cache of the BlueGene/L Supercomputer Processor Node abstract BlueGene/L is a supercomputer consisting of 64K dual-processor system-on-a-chip compute nodes, capable of delivering an arithmetic peak performance of 5.6Gflops per node. To match the memory speed to the high compute performance, the system implements an aggressive three-level on-chip cache hierarchy for each node. The implemented hierarchy offers high bandwidth and integrated prefetching on cache hierarchy levels 2 and 3 to reduce memory access time. The integrated L3-cache stores a total of 4MB of data, using multibank embedded DRAM. The 1024 bit wide data port of the embedded DRAM provides 22.4GB/s bandwidth to serve the speculative prefetching demands of the two processor cores and the Gigabit Ethernet DMA engine. Martin Ohmacht, Dirk Hoenicke, Ruud A. Haring, Alan Gara	SBAC-PAD	4
2004	Unlocking the Performance of the BlueGene/L Supercomputer abstract The BlueGene/L supercomputer is expected to deliver new levels of application performance by providing a combination of good single-node computational performance and high scalability. To achieve good single-node performance, the BlueGene/L design includes a special dual floating-point unit on each processor and the ability to use two processors per node. BlueGene/L also includes both a torus and a tree network to achieve high scalability. We demonstrate how benchmarks and applications can take advantage of these architectural features to get the most out of BlueGene/L. Gheorghe Almási 0001, Siddhartha Chatterjee, Alan Gara, John A. Gunnels, Manish Gupta 0002, Amy Henning, José E. Moreira, Robert Walkup	SC	3
2004	QCDOC: A 10 Teraflops Computer for Tightly-Coupled Calculations abstract Numerical simulations of the strong nuclear force, known as quantum chromodynamics or QCD, have proven to be a demanding, forefront problem in high-performance computing. In this report, we describe a new computer, QCDOC (QCD On a Chip), designed for optimal price/performance in the study of QCD. QCDOC uses a six-dimensional, low-latency mesh network to connect processing nodes, each of which includes a single custom ASIC, designed by our collaboration and built by IBM, plus DDR SDRAM. Each node has a peak speed of 1Gigaflops and two 12,288node, 10+ Teraflops machines are to be completed in the fall of 2004. Currently, a 512 node machine is running, delivering efficiencies as high as 45% of peak on the conjugate gradient solvers that dominate our calculations and a 4096-node machine with a cost of $1.6M is under construction. This should give us a price/performance less than $1per sustained Megaflops. Peter A. Boyle, Dong Chen 0005, Norman H. Christ, Michael A. Clark, Saul D. Cohen, Zhihua Dong, Alan Gara, Bálint Joó, Chulwoo Jung, Ludmila A. Levkova, Xiaodong Liao, Guofeng Liu, Robert D. Mawhinney, Shigemi Ohta, Konstantin Petrov, Tilo Wettig, Azusa Yamaguchi, Calin Cristian	SC	7
2002	Blue Gene/L, a System-On-A-Chip abstract Summary form only given. Large powerful networks coupled to state-of-the-art processors have traditionally dominated supercomputing. As technology advances, this approach is likely to be challenged by a more cost-effective System-On-A-Chip approach, with higher levels of system integration. The scalability of applications to architectures with tens to hundreds of thousands of processors is critical to the success of this approach. Significant progress has been made in mapping numerous compute-intensive applications, many of them grand challenges, to parallel architectures. Applications hoping to efficiently execute on future supercomputers of any architecture must be coded in a manner consistent with an enormous degree of parallelism. The BG/L program is developing a peak nominal 180 TFLOPS (360 TFLOPS for some applications) supercomputer to serve a broad range of science applications. BG/L generalizes QCDOC, the first System-On-A-Chip supercomputer that is expected in 2003. BG/L consists of 65,536 nodes, and contains five integrated networks: a 3D torus, a combining tree, a Gb Ethernet network, barrier/global interrupt network and JTAG. George S. Almási, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, Alina Deutsch, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, Blake G. Fitch, Joseph Gagliano, Alan Gara, Robert S. Germain, Mark Giampapa, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, T. Jamal-Eddine, Gerard V. Kopcsay, Alphonso P. Lanzetta, Derek Lieber, M. Lu, Mark P. Mendell, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Rick A. Rand, Richard D. Regan, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, Sarabjeet Singh, Peilin Song, Burkhard D. Steinmacher-Burow, Karin Strauss, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, J. Brown, Thomas A. Liebsch, A. Schram, G. Ulsh	CLUSTER	24
2002	An overview of the BlueGene/L Supercomputer abstract This paper gives an overview of the BlueGene/L Supercomputer. This is a jointly funded research partnership between IBM and the Lawrence Livermore National Laboratory as part of the United States Department of Energy ASCI Advanced Architecture Research Program. Application performance and scaling studies have recently been initiated with partners at a number of academic and government institutions,including the San Diego Supercomputer Center and the California Institute of Technology. This massively parallel system of 65,536 nodes is based on a new architecture that exploits system-on-a-chip technology to deliver target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). The machine is scheduled to be operational in the 2004-2005 time frame, at price/performance and power consumption/performance targets unobtainable with conventional architectures. Narasimha R. Adiga, Gheorghe Almási 0001, George S. Almási, Yariv Aridor, Rajkishore Barik, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Waiman Chan, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, K. M. Desai, Alina Deutsch, Tamar Domany, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, C. Christopher Erway, J. Esch, Blake G. Fitch, Joseph Gagliano, Alan Gara, Rahul Garg 0001, Robert S. Germain, Mark Giampapa, Balaji Gopalsamy, John A. Gunnels, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, R. D. Jackson, T. Jamal-Eddine, Gerard V. Kopcsay, Elie Krevat, Manish P. Kurhekar, Alphonso P. Lanzetta, Derek Lieber, L. K. Liu, M. Lu, Mark P. Mendell, A. Misra, Yosef Moatti, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Adam J. Oliner, Vinayaka Pandit, R. B. Pudota, Rick A. Rand, Richard D. Regan, Bradley Rubin, Albert E. Ruehli, Silvius Vasile Rus, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, M. Sharma, Edi Shmueli, Sarabjeet Singh, Peilin Song, Vijay Srinivasan, Burkhard D. Steinmacher-Burow, Karin Strauss, Christopher W. Surovic, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Arun R. Umamaheshwaran, P. Verma, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, W. Barrett, C. Engel, B. Drehmel, B. Hilgart, D. Hill, F. Kasemkhani, David J. Krolak, Chun-Tao Li 0001, Thomas A. Liebsch, James A. Marcella, A. Muff, A. Okomo, M. Rouse, A. Schram, M. Tubbs, G. Ulsh, Charles D. Wait, J. Wittrup, Myung Bae, Kenneth A. Dockser, Lynn Kissel, Mark K. Seager, Jeffrey S. Vetter, K. Yates	SC	33
1997	QCDSP: A Teraflop Scale Massively Parallel Supercomputer abstract We discuss the work of the QCDSP collaboration to build an inexpensive Teraflop scale massively parallel computer suitable for computations in Quantum Chromodynamics (QCD). The computer is a collection of nodes connected in a four dimensional toroidial grid with nearest neighbor bit serial communications. A node is composed of a Texas Instruments Digital Signal Processor (DSP), memory, and a custom made communications and memory controller chip. An 8192 node computer with a peak speed of 0.4 Teraflops is being constructed at Columbia University for a cost of $1.8 Million. A 12,288-node machine with a peak speed of 0.6 Teraflops is being constructed for the RIKEN Brookhaven Research Center. Other computers have been built including a 50 Gigaflop version for Florida State University. Dong Chen 0005, Norman H. Christ, Robert G. Edwards, George Fleming, Alan Gara, Sten Hansen, Chulwoo Jung, Adrian Kahler, Stephen Kasow, Anthony D. Kennedy, Greg Kilcup, Yu Bing Luo, Catalin Malureanu, Robert D. Mawhinney, John Parsons, Jim Sexton, ChengZhong Sui, Pavlos Vranas	SC	6