Sharing the licensed frequency spectrum among mobile network operators (MNOs) is a promising approach to improve licensed spectrum utilization. In this paper, we model and analyze a non-orthogonal spectrum sharing system consisting of seller and buyer MNOs where buyer MNOs can lease several licensed sub-bands from different seller MNOs. All base stations (BSs) owned by a buyer MNO can also utilize various licensed sub-bands simultaneously, which are also used by other buyer MNOs. To reduce the interference that a buyer MNO imposes on one seller MNO sharing its licensed sub-band, this buyer MNO has a limitation on the maximum interference caused to the corresponding seller MNO’s users. We assume each MNO owns its BSs and users whose locations are modeled as two independent homogeneous Poisson point processes. Applying stochastic geometry, we derive expressions for the downlink signal-to-interference-plus-noise ratio coverage probability and the average rate of both seller and buyer networks. The numerical results validate our analysis with simulation and illustrate the effect of the maximum interference threshold on the total sum rate of the network.

We present a resource management framework for load-coupled downlink cellular OFDMA networks considering the load factor of an individual base station (BS) per resource block (RB), i.e., the number of adjacent sub-carriers (SCs), as the variable of interest in the resource management problem. The load factor of a BS per RB, which corresponds to the fraction of active SCs in the BS per RB, is an indicator of the level of resource consumption, and it affects the interference caused to that RB reused in other BSs, and thereby, results in a load-coupled OFDMA system. We first propose two distributed schemes to minimize: (i) the total load factor of the BSs (which would in turn increase the number of supportable users in the system), and (ii) the total downlink transmit power level of the BSs. Then, we derive the necessary and sufficient conditions for checking the feasibility of given target-rate requirements (also referred to as demand vector) for users. Accordingly, an iterative and distributed scheme is proposed to check the feasibility of a given demand vector. Next, for a priority-based load-coupled network, we propose a priority-based gradual removal algorithm to support the maximal number of low-priority users while satisfying the demands of the high-priority users. To evaluate the performance of our proposed schemes for resource management and admission control in load-coupled OFDMA networks, the theoretical investigations are complemented with Monte Carlo simulations.

To improve the spectral efficiency in long-term evolution systems, the resource blocks (RBs) are shared among different cells/base stations (BSs) resulting in interference among the cells/BSs on each RB, although all the sub-carriers (SCs) in an RB may not be used in a cell. Defining the load of a given BS per RB as the fraction of the active SCs in that RB, in this paper, we present a generalized signal-to-interference-and-noise-ratio (SINR) model for downlink users on a given RB. This model considers both the transmit powers of the BSs and the loads of the cells over that RB. Under this load-coupled SINR model, to study the feasibility of a given rate demand vector for users, we formulate an optimization problem of minimizing the total load of the BSs on the RBs. Then, for two different scenarios of feasible and infeasible demand vectors, respectively, we study the load management problem (i.e., minimizing the total load of the BSs on the RBs) and admission control problem (i.e., finding the sub-set of users with maximum cardinality whose demands can be concurrently satisfied), respectively. Our theoretical investigations, which provide guidelines for designing radio resource management methods for load-coupled OFDMA networks, are complemented through Monte Carlo simulations.

The problem of joint load management and admission control (JLAC) in underlay OFDMA-based cognitive radio networks (CRNs) is studied. The fraction of the active sub-carriers in a base station (BS) in each resource block (RB) is defined as the load factor of the BS per RB. In the JLAC problem, we simultaneously minimize the secondary users' outage ratio and the total load factors of the BSs via the RBs, subject to the constraint that the primary users are protected. This problem is a NP-hard problem. We first relax it into a convex optimization problem. Then, by employing the optimal solution to the relaxed JLAC problem, we derive a heuristic algorithm to gradually remove the most adversative secondary users imposing the most interference to the primary users. The performance of the proposed algorithm is studied in terms of the outage ratio of secondary users and the total load factors of the BSs via the RBs through extensive simulations.

Summary Mobile social networks are presenting new opportunities for content dissemination. User location, mobility, and social communities can be used to deliver delay‐tolerant content. Most existing dissemination methods either fail to consider the user's interest in their protocol design or just allow exchange of contents between nodes that have a similar interest. If nodes with similar interest never encounter each other, then contents might not be exchanged with them. In this paper, we propose a method in which user location, mobility, and interest as well as certain limiting factors such as relay buffer size and communication overhead are used to select a set of relays for targeted advertisement distribution. Besides, our method does not depend on nodes with similar interest encountering one another. In the proposed method, a distribution agent exploits user location, mobility, and social networks as well as the interest of destinations to select a group of relays to carry content to the targeted destinations. Users move among social communities and carry advertisements to their peers in other communities. We have also developed an optimization problem for advertisement selection and scheduling. Since the problem is NP‐hard, we propose a heuristic solution. Evaluation of the proposed approach shows that the algorithm is not sensitive to network resource variation and readily outperforms popular methods reported in the literature in terms of delay, delivery ratio, and interest compatibility.

In this paper, the region of SINRs vector for a given user on its assigned sub-carriers (SCs) which corresponds to a given target-rate, is characterized. In doing so, given the user's data rate, the boundary of region of the SINRs vector corresponding to data rate for the user on its assigned SCs is obtained. We show that for a given preference of the user, the point laid on that boundary corresponds to the minimum SINRs vectors for providing the given data rate for the user. Therefore, characterizing the region of SINRs vector corresponding to the target-rate for each users on their assigned SCs and at the same time characterizing the feasible SINRs region on each SCs (which is a traditional problem and addressed already) enable us to study if a given target-rate vector is admissible or not.

This paper presents a novel circuit optimization technique to reduce soft error rates (SER) of combinational logic circuits in the presence of process variations. We take advantage of gate sizing technique which has been shown to be one of the most effective methods for SER mitigation in digital circuits. A statistical SER (SSER) estimation approach is proposed to be used to prune the circuit graph into a smaller set of candidate gates. Then, we perform incremental statistical sensitivity computations to determine the resizing step that are the largest improvement to circuit SER. The proposed algorithm trades off SER reduction and area overhead. Experimental results on a variety of benchmarks show SER reductions of 67.3% with gate sizing approach, with 5.5% area overheads and delay improvement of 3.2%, on average. The runtimes for the optimization algorithms are on the order of 10 minutes.

Soft error rate (SER) estimation is becoming more and more important since nanometer digital integrated circuits are getting increasingly vulnerable to soft errors. In this paper, a novel approach is proposed for soft error rate analysis of digital combinational circuit considering all masking factors. We introduce a concept called Probabilistic Vulnerability Window (PVW) which is an inference of the necessary conditions for a Single Event Transient (SET) to cause observable errors in the circuit. A computation model is proposed to calculate PVW's for all circuit gate outputs. Using the computation model, the proposed method estimates the soft error rate of the circuit by computing the probabilistic vulnerability windows in a backward approach. Experimental results show that the proposed method increases the SER computation speed by 1000X, with less than 10% accuracy loss when compared to the Monte-Carlo based fault injection methods. The results also show than the proposed approach keeps its efficiency when it is applied for estimating the soft error rate considering various SET's with different initial widths while the runtime of traditional SER estimation methods increases rapidly in such cases.

Mechatronic systems operating in industrial environments are subject to a variety of threats because of harsh conditions. Industrial systems usually use commercial off-the shelf (COTS) equipment which are not robust and safe against hostile conditions and therefore require fault-tolerance considerations. This paper presents a novel and efficient method for online detection of control flow errors, called software-based control flow checking (SCFC). It is implemented purely in software and does not manipulate the hardware architecture of the system. Redundant instructions and signatures are embedded into the program at compile time and are utilized for control flow checking at run time. The signatures of the basic blocks are derived from the program graph. It is shown in the paper that SCFC method can increase single detection capability to 14.7% and the fault coverage to 6.12% averagely in comparison with other methods without any increase in memory and performance overheads. In the paper, besides experimental evaluations, analytical evaluations are also carried out, based on probability principles. The detection ability of each method used is thus computed. These computations verify the experimental results and show that SCFC can detect more errors than other methods suggested in literature. Considering the memory limitations in some (such as space) applications and the trend towards the requirement for faster execution of programs, we suggest a novel metric called fitness parameter which incorporates these. It is a better measure than the previously proposed ones since it considers the fault coverage, the memory overhead and the execution time (performance overhead) of each method simultaneously, as well as the detection capability.

Carbon Nanotube Field Effect Transistors (CNFETs) show great promise as extensions to silicon CMOS. However, CNFET-based circuits will face great fabrication challenges that will translate into important parameter variations and decreased reliability. Hence, asynchronous logic, which is intrinsically more robust to variability, seems an ideal and perhaps unavoidable choice for digital circuits in CNFET technology. This article presents the results on the design and analysis of a CNFET-based implementation of an asynchronous circuit primitive: the Muller C-element. Using a CNFET SPICE model, we evaluate the robustness of CNFET-based C-element in the presence of CNT fabrication-related nonidealities. We investigate a quantitative evaluation of how timing variability impacts the functionality of a C-element and then, extract the necessary delay constraints of the C-element circuit from the signal transition graph specification. Considering the large degrees of spatial correlation observed between the CNFETs fabricated on directionally grown CNTs, a layout technique is exploited to overcome the robustness challenges of a CNFET-based C-element. Extensive Monte Carlo simulations on the proposed technique have demonstrated the effectiveness of the proposed CNFET-based C-element by improving approximately 50X in its robustness in expense of 65% area, 47% delay, and 56% power consumption overheads. Experimental results indicate that implementation of some CNFET-based Quasi Delay Insensitive (QDI) benchmark circuits using the proposed C-element results in significant robustness improvement with negligible power and throughput overheads. As a promising step toward CNFET-based giga-scale integrated circuits, this article shows that the asynchronous logic is an effective approach to design robust integrated circuits in CNFET technology with inherent extreme physical variations.

Carbon nanotube field effect transistors (CNFETs) show great promise as extensions to silicon CMOS. However, imperfections, which are mainly related to carbon nanotubes (CNTs) growth process, result in metallic and nonuniform CNTs leading to significant functional yield reduction. This paper presents a comprehensive technique for statistical functional yield estimation and enhancement of CNFET-based VLSI circuits. Based on experimental data extracted from aligned CNTs, we propose a compact statistical model to estimate the failure probability of a CNFET. Using the proposed failure model, we show that enhancing the CNT synthesis process alone cannot achieve acceptable functional yield for upcoming CNFET-based VLSI circuits. We propose a technique which is based on replacing each transistor by series-parallel transistor structures to reduce the failure probability of CNFETs in the presence of metallic and nonuniform CNTs. The technique is adapted to use single directional independence, which is inherent in aligned CNTs, to enhance the functional yield as validated by theoretical analysis and simulation results. Tradeoffs between failure probability reduction and design overheads such as area and current drive are explored. As demonstrated by extensive simulation results, the proposed technique achieves 80% functional yield in CNFET technology at the cost of 7.5X area and 34% current drive overheads if the CNT density and the fraction of semiconducting CNTs are improved to 200 CNTs per μm and 99.99%, respectively.

An effective workflow application scheduling on shared resources largely contributes to achieving a high performance in Utility Grids. Users share resources and these resources are autonomously managed in these environments. There is no explicit control on allocating resources to application-tasks on the part of users, the fact that results make users fail in optimizing the application make span and allocation cost. In the current paper, a Minimum First-fit Cost-Make span Trade-off (MinFCMT) heuristic algorithm is developed in order to effectively schedule an application in Utility Grids so that the application make span and allocation-cost can be minimized. To evaluate the MinFCMT heuristic algorithm, widespread simulation of the synthetic workflow is exploited. The results show that the MinFCMT algorithm is more effective than the present algorithms due to optimizing the application make span and allocation-cost in a very low runtime.

This paper presents Investigation of Transient Fault Effects in an asynchronous NoC router. The experiment is based on simulation-based fault injection method to assess the fault-tolerant behavior of the asynchronous router. The effort has been accomplished by employing fault injector signal (FIS) in 136 targets. 13600 transient and permanent faults have been injected into the CSP-Verilog model of NoC router. Different fault models such as glitch, cross-talk, SEU, and SET have been applied in this effort to evaluate asynchronous NoC Router. The experimental results have been considered in different aspects to estimate the NoC router's robustness. Although asynchronous designs seem inherently fault-tolerant due to applying handshaking signals, up to 56% of the injected faults result in failure, and about 43% of injected faults are overwritten before turning into errors. Less than 1% of injected faults treat as latent error. Moreover, the failure rate of token generation consumption is higher than token consumption effects.

In many existing synchronization protocols within wireless sensor networks, the effect of routing algorithm in synchronization precision of two remote nodes is not being considered. In several protocols such as SLTP, this issue is considered for local time estimation of a remote node. Cluster creation is according to ID technique. This technique incurs an increase in cluster overlapping and eventually the routing algorithm will be affected and requires more hops to move from one cluster to another remote cluster. In this article, we present L-SYNC method, which creates large degree clusters for wireless sensor networks synchronization. Using large degree clustering, L-SYNC can reduce path hops. Also, LSYNC uses linear regression method to calculate clock offset and skew in each cluster. Therefore, it is capable to compute skew and offset intervals between each node and its head cluster and, in other words, it can estimate the local time of remote nodes in future and past. To estimate the local time for remote nodes, routing algorithm is used and conversion technique is performed in each time changing hop. The fewer L-SYNC hops could increase the precision. Simulation results illustrate that monotonous clustering formation can increase the precision in synchronization. However, more overhead and time period are needed for clustering formation.

This paper evaluates fault-tolerant behavior of an NoC router through simulation-based method. A structural-level VHDL environment has been employed to estimate fault injector signal’s (FIS) effects. Different fault models such as dead clause, stuck-then, micro-operation, crosstalk, and SEU have been injected to evaluate the transient faults ’ effects. According to the results, up to 48 % of the injected faults cause system failure and also about 51 % are overwritten before turning into errors. Less than 1 % of injected faults treat as latent errors. The average of fault latency has been investigated as 194ns. Almost 70%, 31%, and 35 % of injected faults are overwritten in buffer, routing unit, and switch components, respectively. Routing unit is also recognized as the most tenuous component. 1.

Minimizing power consumption is one of the most important objectives in VLSI design. This paper introduces a methodology for the optimization of total power consumption of template based asynchronous circuits via dual Vddassignment, dual Vthassignment and template sizing while maintaining performance requirements. The utilized circuit model is a Timed Petri-net which captures the dynamic behavior of the circuit. These three power reduction techniques are properly encoded in a quantum genetic algorithm and evaluated simultaneously. Experimental results are given for a number of 65 nm related benchmark circuits and show that this method reduces the total power by close to an order of magnitude, with no or negligible performance penalty. From the experimental results, we show that the combination of asynchronous design and three low power techniques is an effective way to achieve low power and high performance circuits.

Asynchronous circuits have many advantages vs synchronous design styles like high performance and lower power consumption; however, there is a drawback of big overhead in handshake circuitry of these circuits. In this paper, we have reduced the amount of these extra circuits by take advantage of some compiler techniques. The compiler methods can be used innovatively to improve the synthesis results in terms of both power consumption and area, since these code motions lead to removing of completion detection and validity check parts of asynchronous designs. To the best of our knowledge this is the first effort in using the compiler pre-synthesis optimizations in asynchronous circuits to reduce the handshake overhead of these circuits in order to reduce the power consumption and area overhead. The approach is superimposed onto Persia synthesis toolset as a pre-synthesis source-to-source transformation phase, and the results show on average 22% and 24% improvement in terms of area and power consumption for asynchronous benchmarks, respectively.

This paper introduces a framework for the minimization of leakage power consumption of asynchronous circuits via using dual threshold voltages technique. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the circuit. We propose a heuristic method based on quantum genetic algorithm which finds the optimal high and low threshold voltage assignment. Experimental results are given for a number of 90 nm ISCAS benchmark circuits. From the experimental results, we show that the combination of asynchronous and multiple threshold voltage design techniques is an effective way to achieve low leakage power budget in high performance asynchronous circuits.

We present a new method for implementing asynchronous FPGA logic cells which are configurable at pipeline level. Previous implementations of the basic elements of these logic cells were based on the pre-charged logic implementation which imposes some limitations on the size of the logic cell due to the stacking problem. To overcome this limitation we propose a novel method for implementing these templates. Our method uses standard single-rail computational circuits. It does not have any stacking problem and is not limited in size. The results show that a 4-input logic cell implemented by this method outperforms a previous 3-input logic cell by 16% in speed and 29% in power with a negligible area overhead.

Asynchronous circuits already have shown their benefits. The main drawback is the lack of powerful CAD and layout generation tools limiting the widespread use of the asynchronous methodology. QDI asynchronous circuits are known as a powerful category of asynchronous circuits targeting performance and power driven design. In this paper we addressed standard cell implementation of the template based QDI circuits utilizing standard layout generation tools. This is achieved by analyzing and removing outer cell isochronic fork constraint which is the main timing constraints limiting the standard layout generation. The isochronic fork free final netlist has 10--20% area overhead in average which is the cost of facilitating the use of standard CAD tools.

Replacing functional units of an extensible processor with reconfigurable fnctional units enhances performance and flexibility ofprocessors to execute custom instructions. That is due to the ability ofreconfigurable fnctional units to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this paper, we develop a heterogeneous architecture for the reconfigurable fnctional unit of an extensible processor. To verify the efficiency of our architecture, we applied it to 8 applications of Mibench. Our experiments show that compared to the similar architectures, ours supports a wide range of custom instructions. In addition, use of the new architecture improves execution time of custom instructions by 20% to 30% on average. Moreover, compared with the previous architecture, area is reduced by 15%.

An efficient adaptive method to perform dynamic voltage and frequency management (DVFM) for minimizing the energy consumption of microprocessor chips is presented. Instead of using a fixed update interval, the proposed DVFM system makes use of adaptive update intervals for optimal frequency and voltage scheduling. The optimization enables the system to rapidly track the workload changes so as to meet soft real-time deadlines. The method, which is based on introducing the concept of an effective deadline, utilizes the correlation between consecutive values of the workload. In practice because the frequency and voltage update rates are dynamically set based on variable update interval lengths, voltage fluctuations on the power network are also minimized. The technique, which may be implemented by simple hardware and is completely transparent from the application, leads to power savings of up to 60% for highly correlated workloads compared to DVFM systems based on fixed update intervals.

This paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to successfully implement a GALS circuit on FPGA are discussed. The library includes clock generators and arbiters, and different port controllers. Different implementations of these circuits and their advantages and disadvantages are explored. At the end we present a GALS Reed-Solomon decoder as a practical example. The results show that the GALS approach improves the performance of the circuit by 11% and reduces the power consumption by 18.7% to 19.6% considering different error rates. On the other hand, the area of the circuit is increased by 51% which is acceptable considering that a pure synchronous circuit including a central controller is decomposed to generate GALS system and 29% of this overhead belongs to distributing controller in different modules. Deploying better decomposition methods can reduce this overhead substantially.

This paper focuses on a clock generation scheme for implementation of GALS circuits on commercial FPGAs which are mostly synchronous. Previously overlooked timing problems of existing pausible clock generators are explored and a novel clock generator is introduced. To validate the proposed solution we implemented the clock generator and a simple port controller on FPGA. In addition, general design considerations to successfully implement a GALS circuit on FPGAs are discussed. At the end we present a GALS Reed-Solomon decoder as a practical example. The results show that the GALS approach can improve both power and performance of the system using different partitioning strategies.

In this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating actions are modeled in Verilog HDL as abstract actions.