Demo Data from EDBT 2026 / reviewers in the wild / expert
Jonathan Chew
dblp:81/6825
· DBLP profile ↗
4ranked-venue papers
0as first author
0since 2021 · last 2010
0000-0001-7904-6631ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3Software engineering, systems software and programming languages · 2Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Memory systems · 64% Parallel and multicore computing · 30% Distributed systems · 6% | |
| Software engineering, system software, and programming languages
3 papers |
Operating systems · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Operating systems › resource management › memory management
virtual memory |
0.0 | 2 | 1988 | Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures · IEEE Trans. Computers 1988 Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures · ASPLOS 1987 |
Parallel and multicore computing › multiprocessor system
multiprocessor operating systems |
0.0 | 2 | 1988 | Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures · IEEE Trans. Computers 1988 Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures · ASPLOS 1987 |
Operating systems › resource management › memory management › virtual memory
paging |
0.0 | 1 | 1988 | Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures · IEEE Trans. Computers 1988 |
Memory systems › shared memory
distributed shared memory |
0.0 | 1 | 1988 | Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures · IEEE Trans. Computers 1988 |
Operating systems › multiprocessing
multiprocessor operating system |
0.0 | 1 | 1987 | The Duality of Memory and Communication in the Implementation of a Multiprocessor Operating System · SOSP 1987 |
Memory systems › memory management
memory management unit |
0.0 | 1 | 1987 | Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures · ASPLOS 1987 |
Memory systems › memory management
virtual memory |
0.0 | 1 | 1987 | Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures · ASPLOS 1987 |
Distributed systems › operating system support
interprocess communication |
0.0 | 1 | 1987 | The Duality of Memory and Communication in the Implementation of a Multiprocessor Operating System · SOSP 1987 |
Methods — techniques the papers use, named apart from their topics
architecture-independent design · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | Dynamic workload characterization for power efficient scheduling on CMP systemsabstractRuntime characteristics of individual threads (such as IPC, cache usage, etc.) are a critical factor in making efficient scheduling decisions in modern chip-multiprocessor systems. They provide key insights into how threads interact when they share processor resources, and affect the overall system power and performance efficiency. In this paper, we propose and implement mechanisms and policies for a commercial OS scheduler and load balancer which incorporates thread characteristics, and show that it results in improvements of up to 30% in performance per watt. Gaurav Dhiman 0001, Vasileios Kontorinis, Dean M. Tullsen, Tajana Rosing, Eric Saxe, Jonathan Chew |
ISLPED | 6 |
| 1988 | Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor ArchitecturesabstractThe authors describe the design, implementation, and evaluation of the Mach virtual-memory management system. The Mach virtual-memory system exhibits architecture independence, multiprocessor and distributed system support, and advanced functionality. The performance of this virtual-memory system is shown to often exceed that of commercially developed memory management systems targeted at specific hardware architectures.> Richard F. Rashid, Avadis Tevanian, David B. Golub, Robert V. Baron, David L. Black 0001, William J. Bolosky, Jonathan Chew |
IEEE Trans. Computers | 8 |
| 1987 | Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor ArchitecturesabstractThis paper describes the design and implementation of virtual memory management within the CMU Mach Operating System and the experiences gained by the Mach kernel group in porting that system to a variety of architectures. As of this writing, Mach runs on more than half a dozen uniprocessors and multiprocessors including the VAX family of uniprocessors and multiprocessors, the IBM RT PC, the SUN 3, the Encore MultiMax, the Sequent Balance 21000 and several experimental computers. Although these systems vary considerably in the kind of hardware support for memory management they provide, the machine-dependent portion of Mach virtual memory consists of a single code module and its related header file. This separation of software memory management from hardware support has been accomplished without sacrificing system performance. In addition to improving portability, it makes possible a relatively unbiased examination of the pros and cons of various hardware memory management schemes, especially as they apply to the support of multiprocessors. Richard F. Rashid, Avadis Tevanian, David B. Golub, Robert V. Baron, David L. Black 0001, William J. Bolosky, Jonathan Chew |
ASPLOS | 8 |
| 1987 | The Duality of Memory and Communication in the Implementation of a Multiprocessor Operating SystemabstractMach is a multiprocessor operating system being implemented at Carnegie-Mellon University. An important component of the Mach design is the use of memory objects which can be managed either by the kernel or by user programs through a message interface. This feature allows applications such as transaction management systems to participate in decisions regarding secondary storage management and page replacement. Avadis Tevanian, Richard F. Rashid, David B. Golub, Jeffrey L. Eppinger, Jonathan Chew, William J. Bolosky, David L. Black 0001, Robert V. Baron |
SOSP | 6 |