Real-time anomaly detection at the Large Hadron Collider (LHC) requires ultra-low-latency inference under strict computational constraints. This paper presents the FPGA implementation of Spiking Neural Network AutoEncoders (SNN-AEs) for anomaly detection at the trigger level. Multiple SNN-AE architectures are synthesized on Xilinx UltraScale+ FPGAs and their resource utilization is characterized. Event-based spike processing reduces DSP usage by 67% and LUT usage by 53% compared to conventional Deep NN implementations while maintaining Area Under Curve (AUC) = 0.899 for charged Higgs-like scalar (h+) detection. The smallest SNN-AE architecture consumes only 1.99% LUTs and 1.94% DSPs, enabling viable integration into existing L1 trigger systems. Using the Compact Muon Solenoid (CMS) ADC2021 dataset, hardware resource comparisons are provided with FPGA-deployed DNN AutoEncoders across multiple signal models and architectural configurations.

This live demonstration relates to our paper titled "Smart Watchdog Mechanism for Fault Detection in RISC-V" also published at ISCAS 2025. Spiking neural networks (SNNs) can realise low power and area implementations compared to traditional neural network models. We present an interactive demonstration of a SNN-based smart watchdog circuit capable of real-time monitoring and detection of errors during program execution in a modern RISC-V processor. The smart watchdogs performance is demonstrated by monitoring the RISC-V core running a control task resembling a safety-critical application, where demo-attendees can inject faults into the program counter register and witness the detection of errors and how control flow errors impacts the motor operation. The demo permits various fault injection patterns, i.e. bit flips and stuck at zero/one faults.

Modern micro-processors face reliability challenges due to manufacturing defects, aging or when operating in harsh environments like deep-sea or space. Watchdog mechanisms are essential for detecting both permanent and transient faults, but they must exhibit minimal overheads in terms of power and area consumption. Nonetheless, additional research is required to ensure the dependability of the watchdog circuit as if compromised, could pose a significant threat to the system. This paper proposes a smart watchdog paradigm based on spiking neural networks (SNNs) that could realise a reliable, low power and area efficient solution. The smart watchdog presented in this paper was trained to monitor control flow at the execute stage of a RISC-V processor with results showing high fault coverage of 98%, independent of the software application executed. The smart watchdog was able to detect faults not recognised by the trap handler of the RISC-V core. An FPGA implementation of the smart watchdog validates the in-circuit fault detection capability when deployed with a RISC-V processor.

Despite rapid advances in medical technology, cardiac diseases remain the leading cause of global mortality, with arrhythmias that pose significant diagnostic and treatment challenges. This survey presents a comprehensive review of 176 state-of-the-art contributions in machine learning (ML), federated learning (FL), TinyML, and hardware acceleration for efficient, real-time, and privacy-preserving cardiac diagnosis and care. Explores both software and hardware advancements, including differential privacy (DP), quantized neural networks, and FPGA (Field Programmable Gate Array)-based implementations optimized for edge devices and wearable devices. Key challenges, such as latency, energy constraints, adversarial robustness, and personalization, are systematically examined. The survey synthesizes solutions across algorithmic innovations, secure and adaptive FL frameworks, and neuromorphic and sparse architectures, especially FPGA-based solutions, for resource-aware inference and training. Informed by original research, it highlights emerging directions: AI-driven data mining, DP for quantized models, continual learning (CL) on the edge, FPGA-accelerators including quantized DNN, SNN, and Sparse architectures, tuneable/reconfigurable FPGA-based TinyDPFL, Multimodal heterogeneous FL, real-time adversarial detection via model watermarking. This work offers a unified system-level perspective bridging ML algorithms and edge AI hardware, guiding the development of scalable, adaptive, and trustworthy cardiac healthcare systems. Beyond surveying existing literature, it proposes forward-looking design principles to advance intelligent, secure, and practical digital cardiology.

Failure of large complex structures such as buildings and bridges can have monumental repercussions such as human mortality, environmental destruction and economic consequences. It is therefore paramount that detection of structural damage or anomalies are identified and managed early. This highlights the need to develop automated Structural Health Monitoring (SHM) systems that can continuously allow the safety status of structures to be determined, even in the worst and most isolated conditions, to ultimately help prevent destruction and save lives. Signal processing is a crucial step to detecting structural anomalies and recent work demonstrates the opportunities for neural networks, however the encoding of data for SHM requires the extraction of features due to often, noisy data. This paper focuses on feature extraction methods for artificial neural networks (ANNs) and spiking neural networks (SNNs) and aims to identify bespoke features which enable SNNs to encode data and perform the classification of anomalies. Results show that extraction of particular features in large real-world applications improve the classification accuracy of SNNs.

This paper presents a sensory fusion neuromorphic dataset collected with precise temporal synchronization using a set of Address-Event-Representation sensors and tools. The target application is the lip reading of several keywords for different machine learning applications, such as digits, robotic commands, and auxiliary rich phonetic short words. The dataset is enlarged with a spiking version of an audio-visual lip reading dataset collected with frame-based cameras. LIPSFUS is publicly available and it has been validated with a deep learning architecture for audio and visual classification. It is intended for sensory fusion architectures based on both artificial and spiking neural network algorithms.

The current global pandemic due to Severe Acute Respiratory Syndrome Coronavirus 2 (SARS-CoV-2) has taken a substantial number of lives across the world. Although few vaccines have been rolled-out, a number of vaccine candidates are still under clinical trials at various pharmaceutical companies and laboratories around the world. Considering the intrinsic nature of viruses in mutating and evolving over time, persistent efforts are needed to develop better vaccine candidates. In this study, various immuno-informatics tools and bioinformatics databases were deployed to derive consensus B-cell and T-cell epitope sequences of SARS-CoV-2 spike glycoprotein. This approach has identified four potential epitopes which have the capability to initiate both antibody and cell-mediated immune responses, are non-allergenic and do not trigger autoimmunity. These peptide sequences were also evaluated to show 99.82% of global population coverage based on the genotypic frequencies of HLA binding alleles for both MHC class-I and class-II and are unique for SARS-CoV-2 isolated from human as a host species. Epitope number 2 alone had a global population coverage of 98.2%. Therefore, we further validated binding and interaction of its constituent T-cell epitopes with their corresponding HLA proteins using molecular docking and molecular dynamics simulation experiments, followed by binding free energy calculations with molecular mechanics Poisson-Boltzmann surface area, essential dynamics analysis and free energy landscape analysis. The immuno-informatics pipeline described and the candidate epitopes discovered herein could have significant impact upon efforts to develop globally effective SARS-CoV-2 vaccines.

The significant decline in the cost of genome sequencing has dramatically changed the typical bioinformatics pipeline for analysing sequencing data. Where traditionally, the computational challenge of sequencing is now secondary to genomic data analysis. Short read alignment (SRA) is a ubiquitous process within every modern bioinformatics pipeline in the field of genomics and is often regarded as the principal computational bottleneck. Many hardware and software approaches have been provided to solve the challenge of acceleration. However, previous attempts to increase throughput using many-core processing strategies have enjoyed limited success, mainly due to a dependence on global memory for each computational block. The limited scalability and high energy costs of many-core SRA implementations pose a significant constraint in maintaining acceleration. The Networks-On-Chip (NoC) hardware interconnect mechanism has advanced the scalability of many-core computing systems and, more recently, has demonstrated potential in SRA implementations by integrating multiple computational blocks such as pre-alignment filtering and sequence alignment efficiently, while minimizing memory latency and global memory access. This article provides a state of the art review on current hardware acceleration strategies for genomic data analysis, and it establishes the challenges and opportunities of utilizing NoCs as a critical building block in next-generation sequencing (NGS) technologies for advancing the speed of analysis.

Spiking astrocyte neural networks (SANN) are a new computational paradigm that exhibit enhanced self-adapting and reliability properties. The inclusion of astrocyte behaviour increases the computational load and critically the number of connections, where each astrocyte typically communicates with up to 9 neurons (and their associated synapses) with feedback pathways from each neuron to the astrocyte. Each astrocyte cell also communicates with its neighbouring cell resulting in a significant interconnect density. The substantial level of parallelisms in SANNs lends itself to acceleration in hardware, however, the challenge in accelerating simulations of SANNs firmly resides in scalable interconnect and the ability to inject and retrieve data from the hardware. This paper presents a novel multi-FPGA acceleration architecture, AstroByte, for the speedup of SANNs. AstroByte explores Networks-on-Chip (NoC) routing mechanisms to address the challenge of communicating both spike event (neuron data) and numeric (astrocyte data) across significant interconnect pathways between astrocytes and neurons. AstroByte also exploits the NoC interconnect to inject data and retrieve runtime data from the accelerated SANN simulations. Results show that AstroByte can simulate SANN applications with speedup factors of between xl62 -xl88 over Matlab equivalent simulations.

Astrocytes can affect neuronal communication by controlling extracellular ionic concentration levels. In the hippocampus, astrocytes have an intimate relationship with neuronal synapses, enwrapping the synapse tightly to prevent chemical diffusion between synapses, a phenomenon known as semi-isolated synapses. Calcium (Ca2+) is known to enhance neurotransmitter release at excitatory synapses and release is dependent on levels of Ca2+in the perisynaptic environment. Astrocytes have a great influence on Ca2+levels at semi-isolated synapses, thus, they can affect neuronal transmission through control of synaptic Ca2+levels. The perisynaptic astrocytic processes that semi-isolate synapses are exceedingly thin, typically having a diameter less than 100nm, therefore, these processes are most likely devoid of intracellular organelles and therefore, Ca2+stores. Astrocytes possess many transmembrane proteins that can traffic Ca2+into and out of the cell, with the plasma membrane ATPase and the sodium/calcium exchanger being the main transporters capable of carrying Ca2+across the plasma membrane in large quantities.The main aim of this research is to capture a more complete astroglial Ca2+pathway as this may be important for understanding biological processes involving Ca2+such as synaptic transmission, plasticity and ultimately learning. We use a computational approach to capture the ionic dynamics in a semi-isolated synapse, with particular focus on Ca2+dynamics. The model presented here is an extension of a recently published model that hypothesises the formation of Ca2+microdomains in perisynaptic astrocytes. We take this hypothesis further and show that these Ca2+microdomains can act as a local supply of Ca2+to the synaptic cleft during periods of sustained excitability.

Networks-on-Chip (NoC) is the most modular and scalable solution for next generation hardware communication where significant data traffic loads are shared across many communication paths. One key challenge in maximising NoC performance is traffic congestion. The management of congestion at the earliest stage can significantly minimize the impact on NoC throughput. Prediction of NoC congestion offers a pre-emptive strategy in maximising NoC throughput. This paper proposes a novel spiking neural network (SNN) approach to prediction of traffic congestion. The proposed SNN exploits the temporal nature of the traffic to identify congestion patterns. The proposed SNN explores two models and both are trained and evaluated to predict local congestion 30 clock cycles in advance of occurring. Results shows that the SNN predictor utilizes 9 times less hardware area than previous approaches and can achieved up to 96.59% in accuracy.

It is now known that astrocytes modulate the activity at the tripartite synapses where indirect signaling via the retrograde messengers, endocannabinoids, leads to a localized self-repairing capability. In this paper, a self-repairing spiking astrocyte neural network (SANN) is proposed to demonstrate a distributed self-repairing capability at the network level. The SANN uses a novel learning rule that combines the spike-timing-dependent plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules (hereafter referred to as the BSTDP rule). In this learning rule, the synaptic weight potentiation is not only driven by the temporal difference between the presynaptic and postsynaptic neuron firing times but also by the postsynaptic neuron activity. We will show in this paper that the BSTDP modulates the height of the plasticity window to establish an input-output mapping (in the learning phase) and also maintains this mapping (via self-repair) if synaptic pathways become dysfunctional. It is the functional dependence of postsynaptic neuron firing activity on the height of the plasticity window that underpins how the proposed SANN self-repairs on the fly. The SANN also uses the coupling between the tripartite synapses and γ -GABAergic interneurons. This interaction gives rise to a presynaptic neuron frequency filtering capability that serves to route information, represented as spike trains, to different neurons in the subsequent layers of the SANN. The proposed SANN follows a feedforward architecture with multiple interneuron pathways and astrocytes modulate synaptic activity at the hidden and output neuronal layers. The self-repairing capability will be demonstrated in a robotic obstacle avoidance application, and the simulation results will show that the SANN can maintain learned maneuvers at synaptic fault densities of up to 80% regardless of the fault locations.

Forest fires is one of the main causes of environmental degradation and its detection and forecasting is challenging. A novel method of forest fire detection based on spiking neural networks is proposed in this paper. Data obtained from controlled experiments are used as input training samples and a detection model is established by considering the factors of temperature, humidity, carbon monoxide concentration, wind speed and wind direction. Experimental results show that the spiking neural network can achieve a detection accuracy of ∼91%, and therefore provides a better power/accuracy trade-off against existing approaches.

Spiking Astrocyte-neuron Networks (SANNs) model the adaptive/repair feature of the human brain. They integrate astrocyte cells with spiking neurons to facilitate a distributed and fine-grained self-repair capability at the synapse level. SANNs are more complex with the addition of astrocyte cells and require longer simulation times, as they are dynamic over much longer time-scales than traditional neural networks. Therefore, dedicated FPGA accelerators offer reductions in simulation times. To support the acceleration of SANNs, the capability of fault injection to synapses and monitoring significant levels of neuron and astrocyte data for off-chip transmission to PC-based analysis, are required. This paper presents an FPGA-based monitoring platform (FMP) for injecting faults and capturing and analyzing data acquired from the SANN FPGA accelerator, Astrobyte. The FMP uses custom logic and a NIOS II based system to control fault injection and data monitoring on the FPGA. Results show accurate accelerated simulations of fault injection scenarios using FMP with speedups up to 65 times greater compared with equivalent Matlab implementations.

A biophysical model that captures molecular homeostatic control of ions at the perisynaptic cradle (PsC) is of fundamental importance for understanding the interplay between astroglial and neuronal compartments. In this paper, we develop a multi-compartmental mathematical model which proposes a novel mechanism whereby the flow of cations in thin processes is restricted due to negatively charged membrane lipids which result in the formation of deep potential wells near the dipole heads. These wells restrict the flow of cations to "hopping" between adjacent wells as they transverse the process, and this surface retention of cations will be shown to give rise to the formation of potassium (K+) and sodium (Na+) microdomains at the PsC. We further propose that a K+ microdomain formed at the PsC, provides the driving force for the return of K+ to the extracellular space for uptake by the neurone, thereby preventing K+ undershoot. A slow decay of Na+ was also observed in our simulation after a period of glutamate stimulation which is in strong agreement with experimental observations. The pathological implications of microdomain formation during neuronal excitation are also discussed.

The ability of astrocytes to rapidly clear synaptic glutamate and purposefully release the excitatory transmitter is critical in the functioning of synapses and neuronal circuits. Dysfunctions of these homeostatic functions have been implicated in the pathology of brain disorders such as mesial temporal lobe epilepsy. However, the reasons for these dysfunctions are not clear from experimental data and computational models have been developed to provide further understanding of the implications of glutamate clearance from the extracellular space, as a result of EAAT2 downregulation: although they only partially account for the glutamate clearance process. In this work, we develop an explicit model of the astrocytic glutamate transporters, providing a more complete description of the glutamate chemical potential across the astrocytic membrane and its contribution to glutamate transporter driving force based on thermodynamic principles and experimental data. Analysis of our model demonstrates that increased astrocytic glutamate content due to glutamine synthetase downregulation also results in increased postsynaptic quantal size due to gliotransmission. Moreover, the proposed model demonstrates that increased astrocytic glutamate could prolong the time course of glutamate in the synaptic cleft and enhances astrocyte-induced slow inward currents, causing a disruption to the clarity of synaptic signalling and the occurrence of intervals of higher frequency postsynaptic firing. Overall, our work distilled the necessity of a low astrocytic glutamate concentration for reliable synaptic transmission of information and the possible implications of enhanced glutamate levels as in epilepsy.

Recent research has shown that a glial cell of astrocyte underpins a self-repair mechanism in the human brain, where spiking neurons provide direct and indirect feedbacks to presynaptic terminals. These feedbacks modulate the synaptic transmission probability of release (PR). When synaptic faults occur, the neuron becomes silent or near silent due to the low PR of synapses; whereby the PRs of remaining healthy synapses are then increased by the indirect feedback from the astrocyte cell. In this paper, a novel hardware architecture of Self-rePAiring spiking Neural NEtwoRk (SPANNER) is proposed, which mimics this self-repairing capability in the human brain. This paper demonstrates that the hardware can self-detect and self-repair synaptic faults without the conventional components for the fault detection and fault repairing. Experimental results show that SPANNER can maintain the system performance with fault densities of up to 40%, and more importantly SPANNER has only a 20% performance degradation when the self-repairing architecture is significantly damaged at a fault density of 80%.

We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. The system maintains effective functional behavior with a loss of up to 90% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware footprints with the repair unit which consumes only 0.8215% of the complete design and therefore supports scalable implementations. Additionally, the impact on power consumption of the design is also minimal (1.371W). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.

A self-repairing robot utilising a spiking astrocyte-neuron network is presented in this paper. It uses the output spike frequency of neurons to control the motor speed and robot activation. A software model of the astrocyte-neuron network previously demonstrated self-detection of faults and its self-repairing capability. In this paper the application demonstrator of mobile robotics is employed to evaluate the fault-tolerant capabilities of the astrocyte-neuron network when implemented in a hardware-based robotic car system. Results demonstrated that when 20% or less synapses associated with a neuron are faulty, the robot car can maintain system performance and complete the task of forward motion correctly. If 80% synapses are faulty, the system performance shows a marginal degradation, however this degradation is much smaller than that of conventional fault-tolerant techniques under the same levels of faults. This is the first time that astrocyte cells merged within spiking neurons demonstrates a self-repairing capabilities in the hardware system for a real application.

A Self-rePAiring spiking Neural NEtwoRk (SPANNER) hardware architecture is presented in this paper. It is based on a software model of an astrocyte-neuron network which previously demonstrated the ability to self-detect faults and self-repair autonomously. Experimental results in this paper show that when faults occur at the synapse, remaining healthy synapses of the same neuron are enhanced by the feedback from the astrocyte, which enables system functionality to be maintained. This is the first time that astrocyte cells merged within spiking neurons demonstrate a self-repairing capability in hardware. This repair capability achieves a much more finegrained repair capability in hardware compared to the conventional fault tolerance techniques.

Fault tolerance and adaptive capabilities are challenges for modern networks-on-chip (NoC) due to the increase in physical defects in advanced manufacturing processes. Two novel adaptive routing algorithms, namely coarse and fine-grained (FG) look-ahead algorithms, are proposed in this paper to enhance 2-D mesh/torus NoC system fault-tolerant capabilities. These strategies use fault flag codes from neighboring nodes to obtain the status or conditions of real-time traffic in an NoC region, then calculate the path weights and choose the route to forward packets. This approach enables the router to minimize congestion for the adjacent connected channels and also to bypass a path with faulty channels by looking ahead at distant neighboring router paths. The novelty of the proposed routing algorithms is the weighted path selection strategies, which make near-optimal routing decisions to maintain the NoC system performance under high fault rates. Results show that the proposed routing algorithms can achieve performance improvement compared to other state of the art works under various traffic loads and high fault rates. The routing algorithm with FG look-ahead capability achieves a higher throughput compared with the coarse-grained approach under complex fault patterns. The hardware area/power overheads of both routing approaches are relatively low which does not prohibit scalability for large-scale NoC implementations.

Face detection is one of the most active research areas in computer vision. Despite the well documented success of classical machine learning techniques in controlled situations, face detection in completely uncontrolled settings remains a difficult task. Recent progress with bio-inspired approaches have addressed challenging areas of invariance including scale, occlusion and illumination issues, but there remains a lack of concentrated effort into truly multi-view detection of faces in different poses and orientations. This paper introduces a novel strategy to address this through the enhanced implementation of a hierarchical bio-inspired HMAX framework using spiking neurons that implements feature extraction with unsupervised STDP. A multiple trial training scheme is introduced to train separate pools of neurons on different face poses. The trained neurons are then processed by an additional STDP mechanism to generate a streamlined repository of broadly tuned multi-view neurons. Experimental results demonstrate that the new system achieves robust invariant detection of in-plane and out-of-plane rotated faces with single face per image datasets. In addition, extending the multi-view system by introducing lateral inhibition between merged pools of multi-view face detecting neurons, results in a single model that is able to achieve simultaneous face detection and accurate face pose estimation.

A key requirement for modern large scale neuromorphic systems is the ability to detect and diagnose faults and to explore self-correction strategies. In particular, to perform this under area-constraints which meet scalability requirements of large neuromorphic systems. A bio-inspired online fault detection and self-correction mechanism for neuro-inspired PID controllers is presented in this paper. This strategy employs a fault detection unit for online testing of the PID controller; uses a fault detection manager to perform the detection procedure across multiple controllers, and a controller selection mechanism to select an available fault-free controller to provide a corrective step in restoring system functionality. The novelty of the proposed work is that the fault detection method, using synapse models with excitatory and inhibitory responses, is applied to a robotic spike-based PID controller. The results are presented for robotic motor controllers and show that the proposed bio-inspired self-detection and self-correction strategy can detect faults and re-allocate resources to restore the controller's functionality. In particular, the case study demonstrates the compactness (~1.4% area overhead) of the fault detection mechanism for large scale robotic controllers.

Abstract An authentication strategy is proposed in this paper for embedded system software copyright protection. It employs a chaotic coupled map lattices (CML) system to generate the pseudo‐random numbers, which are used to construct message authentication codes (MAC) for embedded system authentication. The CML has multiple lattices where the adjacent lattices have coupled effect. When the system initial condition (e.g. lattice values and system parameters) has a marginal change, the output will have a significant change. Therefore, the proposed scheme is highly secure as the final MAC is almost impossible to be compromised. The experiment is conducted on the platform of field programmable gate array, and its corresponding results demonstrate that the proposed strategy achieved a good security performance, a high computing speed and a relatively low area overhead. Copyright © 2015 John Wiley & Sons, Ltd.

It has been shown that brain-like self-repair can arise from the interactions between neurons and astrocytes where endocannabinoids are synthesized and released from active neurons. This retrograde messenger feeds back to local synapses directly and indirectly to distant synapses via astrocytes. This direct/indirect feedback of the endocannabinoid retrograde messenger results in the modulation of the probability of release (PR) at synaptic sites. When synapses fail, there is a corresponding falloff in the firing activity of the associated neurons, and hence the strength of the direct feedback messenger diminishes. This triggers an increase in PR of healthy synapses, due to the indirect messenger from other active neurons, which is the catalyst for the repair process. In this paper, the repair process is implemented by developing a new learning rule that captures the spike-timing-dependent plasticity and Bienenstock, Cooper, and Munro learning rules. The rule is activated by the increase in PR and results in a potentiation of the weight values, which reestablishes the firing activity of neurons. In addition, this self-repairing mechanism is extended to network-level repair where astrocyte to astrocyte communications are implemented using a linear gap junction model. This facilitates the implementation of an astroglial syncytium involving multiple astrocytes, which relays the indirect feedback messenger to distant neurons: each astrocyte is bidirectionally coupled to neurons. A detailed and comprehensive set of results with analysis is presented demonstrating repair at both cellular and network levels.

A key requirement for modern Networks-on-Chip (NoC) is the ability to detect and diagnose faults and failures. This paper addresses the challenge of fault diagnosis using online testing where the interruption of the runtime operation (performance) under diagnosis is minimised. A novel Monitor Module (MM) is proposed to detect NoC interconnect faults which minimise the intrusion of the regular NoC traffic throughput by (1) using a channel tester which only examines NoC channels when they are idle; and (2) using a testing interval parameter based on the Binary Exponential Back off algorithm to dynamically balance the level of testing when recovering from temporary faults. The paper presents results on the minimal impact on NoC throughput for a range of testing conditions and also highlights the minimal area overhead of the MM (11.56%) compared with an adaptive NoC router implemented on FPGA hardware. Simulation results demonstrate non-intrusion of the NoC runtime traffic throughput when channel are fault free, and also how throughput loss is minimised when faults are identified.

In recent years there has been significant growth in the use of virtual worlds for e-learning. These immersive environments offer enhanced distance learning facilities where students can participate in individual and group activities, using advanced communication tools, inside complex and highly interactive simulations. Video games have entered the mainstream as a popular entertainment format and are starting to be adopted as teaching tools. This paper explores how virtual worlds and video games techniques can be used to create highly immersive and engaging environments for teaching engineering related material. It will show how the presentation layer of remote laboratories, which are traditionally 2-D in nature, could be enhanced by the use of 3-D to facilitate new types of remote interactions and methods of visualizing and interacting with data. The Circuit Warz project is introduced and demonstrates how immersive virtual worlds can be used to create a game based approach to teaching, which supports and complements traditional delivery methods using a collaborative team based competitive format with an underlying hardware infrastructure.

Spiking neural networks (SNNs) attempt to emulate information processing in the mammalian brain based on massively parallel arrays of neurons that communicate via spike events. SNNs offer the possibility to implement embedded neuromorphic circuits, with high parallelism and low power consumption compared to the traditional von Neumann computer paradigms. Nevertheless, the lack of modularity and poor connectivity shown by traditional neuron interconnect implementations based on shared bus topologies is prohibiting scalable hardware implementations of SNNs. This paper presents a novel hierarchical network-on-chip (H-NoC) architecture for SNN hardware, which aims to address the scalability issue by creating a modular array of clusters of neurons using a hierarchical structure of low and high-level routers. The proposed H-NoC architecture incorporates a spike traffic compression technique to exploit SNN traffic patterns and locality between neurons, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Analytical results show the scalability of the proposed H-NoC approach under different scenarios, while simulation and synthesis analysis using 65-nm CMOS technology demonstrate high-throughput, low-cost area, and power consumption per cluster, respectively.

The complexity of inter-neuron connectivity is prohibiting scalable hardware implementations of spiking neural networks (SNNs). Traditional neuron interconnect using a shared bus topology is not scalable due to non-linear growth of neuron connections with the neural network size. This paper presents a novel hierarchical NoC (H-NoC) architecture for SNN hardware which addresses the scalability issue by creating a 3-dimensional array of clusters of neurons with a hierarchical structure of low and high-level routers. The H-NoC architecture also incorporates a spike traffic compression technique to exploit SNN traffic patterns, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Simulation results show a high throughput per cluster (3.33×109spikes/second), and synthesis results using 65-nm CMOS technology demonstrate low cost area (0.587mm2) and power consumption (13.16mW @100MHz) for a single cluster of 400 neurons, which outperforms existing SNN hardware strategies.

Recent work has shown that astrocytes are capable of bidirectional communication with neurons which leads to modulation of synaptic activity. Moreover, indirect signaling pathways of retrograde messengers such as endocannabinoids lead to modulation of synaptic transmission probability. In this paper we hypothesize that this signaling underpins fault tolerance in the brain. In particular, faults manifest themselves in silent or near silent neurons, which is caused by low transmission probability synapses, and the enhancement of the transmission probability of a “faulty” synapse by indirect retrograde feedback is the repair mechanism. Furthermore, based on recent findings we present a model of self repair at the synaptic level, where retrograde signaling via astrocytes increases the probability of neurotransmitter release at damaged or low transmission probability synapses. Although our model is still at the embryo stage, results presented are encouraging and highlight a new research direction on brain-like self repair.

Spiking neural networks (SNNs) are an emerging computing paradigm that attempt to model the biological functions of the human brain. However, as networks approach the biological scale with significantly large numbers of neurons, software simulations face the problem of scalability and increasing computation times. Thus, numerous researchers have targeted hardware implementations in an attempt to more closely replicate the parallel processing capabilities of biological networks. Reconfigurable hardware is seen as a particularly viable platform for attempting to replicate to some degree the natural plasticity and flexibility of the human brain. This paper presents a scalable FPGA based implementation approach that facilitates the accelerated emulation of large-scale SNNs. The approach is validated using a SNN-based edge detection application where an order of magnitude speed performance increase was observed in comparison to a software equivalent implementation.

FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biological neuron/synaptic models. Also their routing structures cannot accommodate the high levels of neuron inter-connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing large scale SNNs on reconfigurable FPGAs. The paper presents a novel Field Programmable Neural Network (FPNN) architecture incorporating low power analogue synapse and a network on chip architecture for SNN routing and configuration. Initial results are presented.

In this paper an area efficient multiplier-less hardware architecture is proposed for the implementation of an integrate- and-fire SNN model. The proposed architecture is intended for large scale implementation on a single FPGA. A modular design is proposed in order to make it flexible. Synaptic multiplication is performed with a simple AND gate, and pulses from different synapses are added together at different times, replicating the accumulation of synaptic inputs for the membrane potential. In order to introduce non-linearity into the membrane potential a normalized random number is introduced to this state variable. The proposed architecture uses spike trains as an input much like those in real networks

Increasingly web based distance education engineering courses are on offer, augmented by the provision of remote experimentation laboratories facilitating distant access to campus based physical resources. The design and implementation of effective and usable remote experimentation facilities poses unique challenges given the inherent complexities of the learning environment and the constraints imposed by the delivery medium. Developments in recent years have addressed many of these issues. However autonomous learning environments by their very nature offer minimal educator assistance and from a students perspective it is inevitable that at some stage of the experimental process, context specific help will be required. This paper seeks to address this issue in the context of remote experimentation for embedded systems and presents a distributed communications application implemented using a web services/.NET Remoting framework for an adaptive intelligent learning environment.

Constant innovation and product evolution in the area of embedded systems necessitates educational institutions and other training providers to continuingly reassess the content and delivery of engineering curricula. Increasingly web based distance education courses are on offer, augmented by the provision of remote experimentation laboratories facilitating distant access to campus based physical resources. The design and implementation of effective and usable remote experimentation facilities poses unique challenges given the inherent complexities of the learning environment and the constraints imposed by the delivery medium. Developments in recent years have addressed many of these issues. However autonomous learning environments by their very nature offer minimal educator assistance. This paper seeks to address this issue in the context of remote experimentation for embedded systems and demonstrates a distributed communications application implemented using a web services/.NET Remoting framework for an adaptive intelligent learning environment for remote experimentation.

The hardware--software (HW--SW) partitioning of applications to dynamically reconfigurable embedded systems allows for customization of their hardware resources during run-time to meet the demands of executing applications. The run-time reconfiguration (RTR) of such systems can have an impact on the HW--SW partitioning strategy and the system performance. It is therefore important to consider approaches to optimally reduce the RTR overhead during the HW--SW partitioning stage. In order to examine potential benefits in performance, it is necessary to develop a method to model and evaluate the RTR. In this paper, a novel method of modeling and evaluating such RTR-reduced HW--SW partitions is presented. The techniques of computation-reconfiguration overlap and the retention of circuitry between reconfigurations are used within this model to explore the possibilities of RTR reduction. The integration of this model into the authors' current genetic-algorithm-driven HW--SW partitioner is also presented, with two applications used to illustrate the benefits of RTR-reduced exploration during HW--SW partitioning.

Embedded systems are an integral part of industrial and domestic electronics necessitating educational institutions and other training providers to offer advanced embedded systems courses. Effective teaching in this area requires an interdependent approach combining theoretical material underpinned by practical laboratory experiments and individualized tutoring. Increasingly the courses on offer include web based distance education packages augmented by the provision of remote experimentation laboratories facilitating distant access to campus based physical resources. The degree of functionality and level of user access to remote laboratories has evolved in recent years expedited by advances in web applications and technologies. This paper details our recent work in this area focusing on the development of architecture for an integrated remote experimentation laboratory designed to meet the unique requirements of a complex, dynamic learning environment.

The use of laboratory experiments is a critically important aspect of engineering education where experience has shown that a complementary approach combining theoretical and practical exercises is vital for effective learning. Increasingly, teaching institutions are offering Web based remote access to distant laboratories as part of an overall e-learning strategy. The design and implementation of effective and usable remote experimentation facilities poses unique challenges given the inherent complexities of the learning environment and the constraints imposed by the delivery medium. Developments in recent years have addressed many of these issues. However autonomous learning environments by their very nature offer minimal educator assistance and from a students perspective it is inevitable that at some stage of the experimental process, context specific help will be required. We address this issue in the context of remote experimentation for embedded systems and present an adaptive intelligent learning environment with intelligent user help.

The use of laboratory experiments is a critically important aspect of engineering education. Experience in teaching has shown that a complementary approach combining theoretical and practical exercises is vital for effective learning. Increasingly, teaching institutions are offering remote access to distant laboratories as part of an overall e-learning strategy. Remote experimentation provided as part of a Web-based learning approach affords a number of critical benefits, allowing flexible access to on-campus resources free of time or geographical constraints. In the context of distance learning it can be the only realistic method of performing experiments. However adapting and redeveloping existing software and hardware resources to this purpose is both time consuming and expensive. An innovative simple approach to this problem is presented in this paper. The remote desktop method offered here allows students to have full access to existing on-campus laboratory resources remotely but without substantial implementation and development overheads incurred by the providers. This is achieved through increased functionality and extended utilisation of existing assets.

The authors propose an evolutionary algorithm (EA) approach to hardware-software partitioning and performance estimation of dynamically reconfigurable embedded systems. A demonstrative application is used to show the effectiveness of the use of GAs to achieve hardware-software partitions with maximum speedup.