This paper presents a Threshold Voltage Generator (TVG) for IoE receivers featuring ULP comparators (CMPs). Prior art TVGs dynamically generate the CMP threshold to enable the receiver to process time-varying received power. However, they require a large area and additional circuits to ensure that the IoE system operates with minimal energy consumption regardless of temperature changes. The proposed TVG has been implemented in a 90-nm STMicroelectronics CMOS technology with a 0.6-V supply, targeting 1-kbps datarate. It occupies 40x less area than RC-based TVGs, consumes 2.2 nA and ensures a 3.5-dB SNR boost without affecting IoE system performances. When compared to previous art, it allows for a 10x energy consumption reduction without requiring any additional circuits. Monte Carlo simulations of an ULP receiver equipped with the proposed TVG show a 0-% Packet Error Rate from -40 °C to +85 °C.

A Threshold Voltage Generator (TVG) circuit for continuous-time comparators is presented. It may be used in ULP IoT systems requiring nanoWatt power consumption, kbps bitrates and the reception of packets with lengths up to hundreds of bits. The circuit is based on a switched capacitor technique to generate the threshold voltage without requiring any large area resistors and with the system clock active only during the reception of data, thus minimizing energy consumption. Latency is also minimized as the threshold is generated within the first received bit of the packet. The reception of packets with no limits on their length is made possible by continuously updating the threshold, which also allows correct operation even in case of amplitude variations in the incoming signal during the data reception. It has been implemented and verified through post-layout simulations in an STMicroelectronics 90-nm CMOS technology with a 0.6-V supply, targeting a 1-kbps bitrate. It occupies an area lower than 0.001 mm2, which is less than 1% of the area of a standard RC-based TVG implemented in the same technology. A prototype of the proposed TVG is currently under fabrication.

Several recent works have shown the advantages of using phase-change memory (PCM) in developing brain-inspired computing approaches. In particular, PCM cells have been applied to the direct computation of matrix-vector multiplications in the analog domain. However, the intrinsic nonlinearity of these cells with respect to the applied voltage is detrimental. In this paper we consider a PCM array as the encoder in a Compressed Sensing (CS) acquisition system, and investigate the effect of the non-linearity of the cells. We introduce a CS decoding strategy that is able to compensate for PCM nonlinearities by means of an iterative approach. At each step, the current signal estimate is used to approximate the average behaviour of the PCM cells used in the encoder. Monte Carlo simulations relying on a PCM model extracted from an STMicrolectronics 90 nm BCD chip validate the performance of the algorithm with various degrees of nonlinearities, showing up to 35 dB increase in median performance as compared to standard decoding procedures.

In this paper we present a reconfigurable Class-E Power Amplifier (PA) whose operation frequency covers all uplink bands of GSM standard. We describe the circuit design strategy to reconfigure PA operation frequency maximizing the efficiency. Two dies, manufactured using CMOS and MEMS technologies, are assembled through bondwires in a SiP fashion. Prototypes deliver 20dBm output power with 38% and 26% drain efficiencies at lower and upper bands, respectively. MEMS technological issues degrading performance are also discussed.

The problems related to the hydrodynamic simulation of semiconductor devices operating at liquid nitrogen temperature are investigated, with emphasis on the numerical aspects. A discretization strategy is proposed that allows one to incorporate in a conventional hydrodynamic program typical low-temperature effects, such as Fermi statistics and incomplete ionization, as well as proper boundary conditions. The suggested technique has been implemented in the hydrodynamic version of the program HFIELDS, and it has been tested by means of the simulation of a submicron n-channel MOSFET.>

A spherical-harmonics expansion method is used to find an approximate numerical solution of the Boltzmann transport equation (BTE) in a 1-D semiconductor device including acoustic and optical phonon, ionized impurity, and impact ionization scattering as well as a system of nonparabolic bands fitting the experimental density of states up to 2.6 eV. The method is applied to the simulation of a 1-D BJT and to the computation of the collector current multiplication factor. A comparison with experimental data is presented.>

An algorithm allowing the automatic generation of a mesh and accounting for the main physical features of the problem is presented. The adaptivity is provided by a refinement strategy which preserves the characteristics of the initial grid, inserting nodes only in the regions where the solution deviates from a linear behavior. A geometrical interpretation in terms of a monitor surface is given, and various different approaches to the problem are discussed. The efficiency of the algorithm is enhanced by a local solution scheme, which uses previously computed values of all the unknown quantities as boundary conditions for the newly generated nodes. A few examples illustrate the performance of the algorithm.>

A discretization scheme is applied to the hydrodynamic model for semiconductor devices that generalizes the Scharfetter-Gummel method to both the momentum-conservation and the energy-conservation equations. The major advantages of the scheme are: (1) the discretization is carried out without neglecting any terms, thus providing a satisfactory description of such effects as velocity overshoot and carrier heating; and (2) the resulting equations lend themselves to a self-consistent solution procedure similar to those currently used to solve the simpler drift-diffusion equations. Two-dimensional steady-state simulations of an n-channel MOSFET and of an n-p-n BJT (bipolar junction transistor) have been carried out by means of an improved version of the program HFIELDS. Carrier-temperature plots have been obtained with a reasonable computational effort, demonstrating the efficiency of this technique. The results have been compared with those obtained with the standard drift-diffusion model and significant differences in the electron concentration have been found, especially at the drain end of the MOSFET channel.>

In this paper we propose a sensitivity-analysis technique for device design. By this method, we determine the linearized variations of the device terminal characteristics following some change either in the impurity distribution, or in device geometry, such as channel length and oxide thickness. This technique has been implemented in our general-purpose two-dimensional device-analysis program (HFIELDS) and proved to be very efficient, as only the assembly of the RHS and one back-substituton is required in order to achieve the final result. It is believed that the present method can be profitably used for both deterministic and statistical device design.