With the rise of large language models, two significant challenges are their high power consumption during training and their black-box nature. The Tsetlin Machine (TM) offers a logic-based, interpretable alternative to traditional Machine Learning (ML) models to address these issues. TM is used in various ML-based edge computing and Internet of Things applications, such as batteryless sensors, resource-constrained intrusion detection, and on-device training. It shows 30.5× reduction in computation cost, 36.6× reduction in storage memory footprint, 13.5× latency and energy reductions, and converges faster than neural networks. It can be implemented on different hardware platforms, including field-programmable gate arrays, superconducting circuits, and memristor-transistor arrays. Filling a gap, we provide a holistic reference containing more than 160 implementations of TMs. In this tutorial and survey, we explain the algorithm of the basic TM in detail with a background of Learning Automata. Next, we discuss different TM variants, including the Regression TM, Federated Learning-based TMs, the Coalesced TM, Real and Integer-Weighted TMs, and the Convolutional TM for text and image classification. We classify these software and hardware implementations based on their algorithmic similarities and compare them using key performance metrics such as accuracy, training time, energy consumption per classification, and operating frequency. Additionally, we discuss our observations on general trends, insights from our comparative analysis, limitations of existing implementations, and potential directions for future research to further extend its applicability in energy-efficient Internet of Things and edge computing applications.

Congestive heart failure (CHF) is an acute syndrome that results from ventricular dysfunction and progresses in four stages. Its timely detection can reverse heart damage and save lives. This work proposes a low-power, computationally efficient VLSI architecture to detect CHF using a single-lead ECG signal for the first time. This architecture employs a novel wavelet function-based electrocardiogram (ECG) feature extraction method and a random forest (RF) classifier, which can classify regular beats from CHF beats using a subject-oriented approach. Using ECG signals from publicly available datasets, BIDMC-CHF and MIT-BIH NSRDB, the proposed architecture achieves 90.5% accuracy, having a power consumption of$0.1~\mu W$when implemented using TSMC 40-nm bulk CMOS technology as an ASIC. The low power consumption of the proposed architecture enables it to be utilized efficiently for real-time ECG analysis in wearable devices.

Ventricular arrhythmia (VA) is the most critical cardiac anomaly among all arrhythmia beats. Thus, it becomes imperative to predict the occurrence of VA to avoid sudden casualties caused by these arrhythmia beats. In the past, only a few hardware designs have been proposed to predict VA using various features derived from electrocardiogram (ECG) signals and processed using machine learning classifiers. However, these designs are either complex or need more prediction accuracy. Therefore, a deep neural network (DNN)-based co-processor for arrhythmia prediction is proposed in this article. It can predict VA at least$15 \ \min $before its occurrence with 91.6% accuracy. Co-processor architecture for arrhythmia prediction (CoAP) uses an optimal feature vector extracted from the ECG signal and an optimized DNN, using a novel approximate multiplier (AM). CoAP operates at 12.5 kHz and consumes$4.69~\mu \text { W}$when implemented using SCL$180\text {-nm}$bulk CMOS technology. The low power realization of the proposed design and its higher accuracy, compared with well-known state-of-the-art methods, make it suitable for wearable devices.

Modulo polynomial multiplication is an essential mathematical operation in the area of finite field arithmetic. Polynomial functions can be represented as tensors, which can be utilized as basic building blocks for various lattice-based post-quantum cryptography schemes. This paper presents a tensor-based novel modulo multiplication method for multivariate polynomials over$GF(2^{m})$and is realized on the hardware platform (FPGA). The proposed method consumes$6.5\times$less power and achieves more than$6\times$speedup compared to other contemporary single variable polynomial multiplication implementations. Our method is embarrassingly parallel and easily scalable for multivariate polynomials. Polynomial functions of nine variables, where each variable is of degree 128, are tested with the proposed multiplier, and its corresponding area, power, and power-delay-area product (PDAP) are presented. The computational complexity of single variable and multivariate polynomial multiplications are$O(n)$and$O(np)$, respectively, where$n$is the maximum degree of a polynomial having$p$variables. Due to its high speed, low latency, and scalability, the proposed modulo multiplier can be used in a wide range of applications.

Lattice-based homomorphic encryption schemes provide strong resistance against quantum and classical computer-based adversary security attacks. In this article, we present a software-hardware co-design of two partially homomorphic encryption (PHE) schemes employing an ARM-System on Chip (ARM-SoC) and an field programmable gate array (FPGA). This provides necessary acceleration to PHE methods in the ecosystem mentioned above. The first PHE scheme is designed for generic homomorphic encryption, while the second scheme is aimed at resource optimized lightweight IoT-driven applications. For seamless assimilation, a robust and reliable low latency data transfer protocol is developed between the FPGA-based accelerator IP and ARM-SoC host system. The proposed PHE schemes are realized using Verilog hardware description language on multiple FPGA platforms. The proposed lightweight scheme is$52.71\times$more resource-efficient than the pipelined BGV RLWE-based method. It exhibits$1.43\times$and$1.29\times$better throughput than non-pipelined and pipelined realizations of the BGV RLWE-based scheme. The proposed hardware accelerators realized on FPGA platforms having lesser clock speed and consuming lower resources showcase significant speedup compared to their software implementations making our proposed method an efficient alternative to enhance security in edge-enabled IoT devices.

Nonvolatile memories, such as resistive random access memory (RRAM), for in-memory computing (IMC), have shown great potential in accelerating neural networks (NNs). However, existing IMC architectures rely on the area and power-hungry analog-to-digital converters (ADCs) for sensing the current, diminishing all the benefits of RRAM. Also, enhancing memory density is essential for implementing compact and efficient artificial intelligence (AI) systems. Implementing multiple states in a single memory cell decreases the resistance between states, making it difficult to sense the current. Thus, incorporating ADCs in multilevel cells (MLCs) further increases the design cost. This article proposes an ADC-less reprogrammable RRAM-based IMC architecture. The ADC-less sensing scheme converts the RRAM array current into its digital equivalent. The proposed scheme can distinguish RRAM resistive states equivalent to 4-bit/cell with a minimal resistance margin of 0.3$\text{K}\Omega $between two consecutive states. It is realized with only 12 transistors, the least among the state-of-the-art designs used in IMC architectures. This article also presents an MLC programming method, resulting in a 22% cycle-to-cycle and device-to-device variation-tolerant design with an average power consumption of$21.5 ~\mu \text{W}$, which is 60.18% less than the contemporary IMC architectures. Furthermore, the proposed current sensor (CS) requires only 12 transistors which is the least among the state-of-the-art works.

Continuous monitoring of the electrical activity of heart signals using wearable Internet of Healthcare Things (IoHTs) devices plays a crucial role in decreasing mortality rates. However, this continuous monitoring using an electrocardiogram (ECG) or vectorcardiogram (VCG) generates huge clinical data. Moreover, these devices are constrained in terms of ON-chip storage, data transmission capacity, and power. Thus, handling a large amount of data is difficult with these devices, making it necessary to compress these data for storage and transmission. Lossless or near-lossless data compression solves this problem, ensuring that no relevant physiological/clinical information is lost in the compression process. Therefore, low-power, resource-efficient, and lossless VLSI architectures are proposed in this article to compress multichannel ECG/VCG data. The designs are tested using the PTB database for both ECG and VCG data and can achieve compression ratios (CRs) of 3.857 and 4.45 with minimal power and area requirements making them suitable for low-power wearable healthcare devices.

Atrial fibrillation (AF) is a recurrent and life-threatening disease leading to rapid growth in the mortality rate due to cardiac abnormalities. It is challenging to manually diagnose AF using electrocardiogram (ECG) signals due to complex and varied changes in its characteristics. In this article, for the first time, an end-to-end edge-enabled machine learning-based VLSI architecture is proposed to classify ECG excerpts having AF from normal beats. Researchers have found that abnormal atrial activity is confined to the low-frequency range through the decades. Therefore, in the proposed work, this frequency band is directly analyzed for AF detection, which has not previously been discussed. The proposed architecture is implemented using 180-nm bulk CMOS technology consuming$11.098~\mu {\mathrm{ W}}$at$25~ {\text {kHz}}$and exhibits an accuracy of 92.37% for class-oriented classification and 81.60% for subject-oriented classification. The low-power realization of the proposed design, as compared to the state-of-the-art methods, makes it suitable to be used for wearable devices.

The work presented in this article focuses on designing a floating MOS-dynamic threshold voltage MOSFET (DTMOS)-based circuit to emulate a memristor. The proposed circuit consists of four transistors, including a DT-MOSFET and an external capacitor, which helps obtain high-frequency operations up to 3 MHz. This facilitates easier integration of the devices and monolithic IC fabrication. The correctness of the proposed emulator is validated by conducting various parametric analyses at different operating frequencies and process corners, and it generates acceptable pinched hysteresis loops (PHLs) at various frequencies. Furthermore, pre- and post-layout validation of the proposed emulator are also performed using Cadence Virtuoso with Taiwan Semiconductor Manufacturing Company (TSMC) 180-nm process design kits (PDKs) to prove its effectiveness as a memristor. The area and power consumption of the proposed emulator are$157.48~\mu \text {m}^{2}$and$8.24~\mu \text {W}$, respectively. The physical experiment of the proposed memristor emulator is performed using ALD$1106~n$-channel MOSFETs to characterize its functionality as a real-life memristor. It is also used in designing a memristor-based application to showcase its applicability in power and area optimal circuit design.

With the increase in the complexity of chip designs, VLSI physical design has become a time-consuming task, which is an iterative design process. Power planning is that part of the floorplanning in VLSI physical design where power grid networks are designed in order to provide adequate power to all the underlying functional blocks. Power planning also requires multiple iterative steps to create the power grid network while satisfying the allowed worst-case IR drop and Electromigration (EM) margin. For the first time, this paper introduces Deep learning (DL)-based framework to approximately predict the initial design of the power grid network, considering different reliability constraints. The proposed framework reduces many iterative design steps and speeds up the total design cycle. Neural Network-based multi-target regression technique is used to create the DL model. Feature extraction is done, and training dataset is generated from the floorplans of some of the power grid designs extracted from IBM processor. The DL model is trained using the generated dataset. The proposed DL-based framework is validated using a new set of power grid specifications (obtained by perturbing the designs used in the training phase). The results show that the predicted power grid design is closer to the original design with minimal prediction error (~2%). The proposed DL- based approach also improves the design cycle time with a speedup of ~6x for standard power grid benchmarks.

With the advancement of technology nodes, Electromigration (EM) signoff has become increasingly difficult, which requires a considerable amount of time for an incremental change in the power grid (PG) network design in a chip. The traditional Black’s empirical equation and Blech’s criterion are still used for EM assessment, which is a time-consuming process. In this article, for the first time, we propose a machine learning (ML) approach to obtain the EM-aware aging prediction of the PG network. We use neural network--based regression as our core ML technique to instantly predict the lifetime of a perturbed PG network. The performance and accuracy of the proposed model using neural network are compared with the well-known standard regression models. We also propose a new failure criterion based on which the EM-aging prediction is done. Potential EM-affected metal segments of the PG network is detected by using a logistic-regression--based classification ML technique. Experiments on different standard PG benchmarks show a significant speedup for our ML model compared to the state-of-the-art models. The predicted value of MTTF for different PG benchmarks using our approach is also better than some of the state-of-the-art MTTF prediction models and comparable to the other accurate models.

As many real-life optimization problems are difficult to solve by exact optimization methods, a number of metaheuristics are developed over the years to search for viable solutions, e.g., river formation dynamics (RFD) algorithm. RFD algorithm is based on the analogy that water drops traverse from source to destination by following a random probabilistic search strategy. This search strategy is employed to solve various optimization problems in practice. However, the search strategy of RFD algorithm lacks theoretical analysis and the convergence property of RFD algorithm needs mathematical reasoning for comprehensive understanding of the working mechanism. In this paper, the random search strategy of RFD algorithm is analyzed mathematically and the convergence property of the algorithm is examined by using Markov chain theory. Several conditions for convergence are showcased and it is proved that RFD algorithm can indeed satisfy these conditions to achieve global optimality efficiently. Further, several experiments are performed on a set of single objective test functions to demonstrate the convergence of RFD algorithm in practice.

The Cooperative Co-evolution framework is an effective approach for decomposing large scale global optimization problems into multiple sub-components. Every subcomponent uses different optimization algorithms which evolve cooperatively and are independent of each other. These subcomponents contribute in a different way to the overall improvement of the optimal solution. Hence, the computation cost can be decreased by separating out the stagnant subcomponents of the population. Therefore, it is appropriate to allocate resources in an intelligent manner to increase the computational efficiency. In this paper, we illustrate a decomposition strategy to solve large scale global optimization problems which is scalable to millions of variables. The proposed strategy improves computational efficiency and enables embracing parallelization. The framework presented in this paper constitutes Cooperative Co-evolution based Genetic Algorithm with Scalar Distance Grouping technique (CCGA-SDG) derived from Cooperative Co-evolution based Genetic Algorithm (CCGA). In our proposed scheme, a novel scalar distance grouping technique is employed that collates the dependent variables together. The stagnant sub-components of the population are detected using this grouping method and resource reallocation is performed accordingly to increase the computational efficiency. Using our proposed methodology, a benchmark function $f_{6}$ of CEC'08 benchmark composed of 10 million variables is evaluated in 1759.79 seconds using 04 processors connected with Message Passing Interface (MPI) exhibiting better accuracy as compared to other methods. Moreover, for ${f}3$ and $f_{6}$ functions we achieve a better accuracy and for rest of the benchmark functions we achieve acceptable solutions.

Over the past decade, several approximate adders have been proposed in the literature based on the design concept ofEqual Segment Adder(ESA). In this approach, an$N$-bit adder is segmented into several smaller and independent equally sized accurate sub-adders. An$N$-bit ESA has two primary design parameters: (i) Segment size ($k$), which represents the maximum length of carry propagation; and (ii) Overlapping bits ($l$), which represents the minimum number of bits used in carry prediction, where$1 \leq k < N$and$0 \leq l < k$. Based on the combinations of$k$and$l$, an$N$-bit ESA has$N(N-1)/2$possible configurations. In this paper, we analyse ESAs and propose analytical models to estimate accuracy, delay, power and area of ESAs. The key features of the proposed analytical models are that: (i) They are generalized, i.e., work for all possible configurations of an$N$-bit ESA; and (ii) They are superior (i.e., estimate more accurately) or at par to the existing analytical models. From the proposed analytical models, we observe that in an$N$-bit ESA, there exist multiple (more than one) configurations which exhibit similar accuracy. However, these configurations exhibit different delay, power and area. Therefore, for a given accuracy, the configurations which provide minimal delay, power and/or area need to be known apriori for efficient, intelligent and goal oriented implementations of ESAs. In this regard, we present an optimization framework that exploits the proposed analytical models to find the optimal configurations of an$N$-bit ESA. Further, we know that accuracy of an ESA does not depend on the adder architecture used to implement it, however, its delay, power and area depend significantly. Consequently, the optimal configurations vary with adder architectures used to implement the ESA. In order to cover a wide range of adders, we consider three types of adder architecture in our analysis: (i) Architectures having smaller area ($O(N)$); (ii) Architectures having smaller delay ($O(log_2N)$); and (iii) Architectures having in-between delay ($O(N/4)$) and area ($O(2N)$).

The gap between domain experts and natural language processing expertise is a barrier to extracting understanding from clinical text. We describe a prototype tool for interactive review and revision of natural language processing models of binary concepts extracted from clinical notes. We evaluated our prototype in a user study involving 9 physicians, who used our tool to build and revise models for 2 colonoscopy quality variables. We report changes in performance relative to the quantity of feedback. Using initial training sets as small as 10 documents, expert review led to final F1scores for the "appendiceal-orifice" variable between 0.78 and 0.91 (with improvements ranging from 13.26% to 29.90%). F1for "biopsy" ranged between 0.88 and 0.94 (-1.52% to 11.74% improvements). The average System Usability Scale score was 70.56. Subjective feedback also suggests possible design improvements.

The concept of approximate computing, that is, to sacrifice computation quality for computation efforts, has recently emerged as a promising design approach. Over the past decade, several research works have explored approximate computing at both the software level and hardware level of abstraction with encouraging results. At the hardware level of abstraction, adders (being the fundamental and most widely used data operators in digital systems) have attracted a significant attention for approximation. In this article, we first explain briefly the need/significance of approximate adders. We then propose four Approximate Full Adders (AFAs) for high-performance energy-efficient approximate computing. The key design objective behind the proposed AFAs is to curtail the length of carry propagation subjected to minimal error rate. Next, we exploit one of the proposed AFAs (optimal one) to construct an N -bit approximate adder that hereinafter is referred as “ApproxADD.” An emergent property of ApproxADD is that carries do not propagate in it, and, consequently, it provides bit-width-aware constant delay ( O (1)). ApproxADD also provides improvement in dynamic power consumption by 46.31% and in area by 28.57% w.r.t. Ripple Carry Adder (RCA), which exhibits the lowest power and area. Although ApproxADD provides a significant improvement in delay, power, and area, it may not be preferred for some of the error-resilient applications because its: (i) Error Distance (ED) is too high; and (ii) Error Rate (ER) increases rapidly with bit-width ( N ). To improve ED and ER, we exploit the concept of carry-lifetime and Error Detection and Correction logic, respectively. In this way, we introduce two more (improved) versions of ApproxADD--ApproxADD υ 1 and ApproxADD. We call these as ApproxADD υ 1 and ApproxADD υ 2 with existing approximate adders based on conventional design metrics and approximate computing design metrics. Furthermore, to inspect effectiveness of the proposed approach in real-life applications, we demonstrate image compression and decompression by replacing the conventional addition operations in Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) modules with ApproxADD υ 2.

Rapid evolution of E-world demands delay, power and area optimized digital circuits/systems while still meeting the security requirements of the cryptography applications. Cryptographic hash functions (which are considered the workhorse of security layers) provide compressive and non-invertible outputs. This signifies that approximate implementation of cryptographic hash functions can provide improvements in delay, power and area without considerable change in security level. In this paper, we first examine likelihood of infusing approximation in cryptographic hash functions and then propose a methodology to evaluate the effects of approximation. Further, we demonstrate four approximate pipelined implementations of Secure Hash Algorithm 1 (SHA-1). Our simulation results show that the proposed approximate pipelined SHA-1s provide significant improvements in delay, power and area with negligible change in security level.

Statutory analysis is a significant component of research on almost any legal issue and determining if a statutory provision applies is an integral part of the analysis. In this paper we present the initial results from an attempt to support the applicability assessment in situations where the number of statutory provisions to be considered is large. We propose the use of a framework in which a single human expert cooperates with a machine learning text classification algorithm. Our experiments show that an adoption of the approach leads to a better performance during the relevance assessment. In addition, we suggest how to re-use a classification model trained during one statutory analysis for another related analysis. This points to a new way of capturing and re-using knowledge produced in the course of statutory analysis. Our experiments confirm the viability of this approach.

Partitioning is an important technique for solving graph based problems. The quality of partitions produced by standard methods, for example Fiduccia and Mattheyses (FM) algorithm, depends on the initial random seed partition. In order to get the best partitions, we have to run the partitioner many times with different seed partitions. In this paper, we present a heuristic for producing good seed partitions for partitioning graphs and hypergraphs by analyzing an appropriately derived resistor, current source electrical network and sorting the nodes according to their potentials. This is feasible because we use a special purpose DC analyzer which is very fast and can handle circuits of size up to a million nodes. Experiments have been performed on IBM benchmark hypergraphs on a Pentium-4 machine having 1GB RAM. For larger size hypergraphs, our method outperforms the standard random seed based FM algorithm both in terms of the partitioning time and in terms of the cut-cost.