Parasitic elements play a major role in advanced circuit design and pose considerable run-time and memory problems for the post-layout verification, especially in the case of full-chip extraction. This brief presents a realizable R(L)C(M)-netlist-in-R(L)C(M)-netlist-out method to sparsify and reduce the capacitive coupling parasitics in circuits with interconnect lines. The method is applicable in conjunction with partitioning-based model-order reduction algorithms to reduce the complete extracted netlists, or as a stand-alone tool to process only the capacitive coupling. It is shown that, by using the method, circuits with even dense capacitive coupling can be partitioned and reduced efficiently.

This paper presents a robust partitioning-based model-order reduction (MOR) method, PartMOR, suitable for reduction of very large RLC circuits or RLC-circuit parts of a non-RLC circuit. The MOR is carried out on a partitioned circuit, which enables the use of low-order moments and macromodels of few elements, while still preserving good accuracy for the reduction. As the method produces a positive-valued, passive, and stable reduced-order RLC circuit (netlist-in-netlist-out), it can be used in conjunction with any standard analysis tool or circuit simulator without modification. It is shown that PartMOR achieves excellent reduction results in terms of accuracy and reduced CPU time for RLC, RC, and RL circuits.