Over the past decade, several approximate adders have been proposed in the literature based on the design concept ofEqual Segment Adder(ESA). In this approach, an$N$-bit adder is segmented into several smaller and independent equally sized accurate sub-adders. An$N$-bit ESA has two primary design parameters: (i) Segment size ($k$), which represents the maximum length of carry propagation; and (ii) Overlapping bits ($l$), which represents the minimum number of bits used in carry prediction, where$1 \leq k < N$and$0 \leq l < k$. Based on the combinations of$k$and$l$, an$N$-bit ESA has$N(N-1)/2$possible configurations. In this paper, we analyse ESAs and propose analytical models to estimate accuracy, delay, power and area of ESAs. The key features of the proposed analytical models are that: (i) They are generalized, i.e., work for all possible configurations of an$N$-bit ESA; and (ii) They are superior (i.e., estimate more accurately) or at par to the existing analytical models. From the proposed analytical models, we observe that in an$N$-bit ESA, there exist multiple (more than one) configurations which exhibit similar accuracy. However, these configurations exhibit different delay, power and area. Therefore, for a given accuracy, the configurations which provide minimal delay, power and/or area need to be known apriori for efficient, intelligent and goal oriented implementations of ESAs. In this regard, we present an optimization framework that exploits the proposed analytical models to find the optimal configurations of an$N$-bit ESA. Further, we know that accuracy of an ESA does not depend on the adder architecture used to implement it, however, its delay, power and area depend significantly. Consequently, the optimal configurations vary with adder architectures used to implement the ESA. In order to cover a wide range of adders, we consider three types of adder architecture in our analysis: (i) Architectures having smaller area ($O(N)$); (ii) Architectures having smaller delay ($O(log_2N)$); and (iii) Architectures having in-between delay ($O(N/4)$) and area ($O(2N)$).

The concept of approximate computing, that is, to sacrifice computation quality for computation efforts, has recently emerged as a promising design approach. Over the past decade, several research works have explored approximate computing at both the software level and hardware level of abstraction with encouraging results. At the hardware level of abstraction, adders (being the fundamental and most widely used data operators in digital systems) have attracted a significant attention for approximation. In this article, we first explain briefly the need/significance of approximate adders. We then propose four Approximate Full Adders (AFAs) for high-performance energy-efficient approximate computing. The key design objective behind the proposed AFAs is to curtail the length of carry propagation subjected to minimal error rate. Next, we exploit one of the proposed AFAs (optimal one) to construct an N -bit approximate adder that hereinafter is referred as “ApproxADD.” An emergent property of ApproxADD is that carries do not propagate in it, and, consequently, it provides bit-width-aware constant delay ( O (1)). ApproxADD also provides improvement in dynamic power consumption by 46.31% and in area by 28.57% w.r.t. Ripple Carry Adder (RCA), which exhibits the lowest power and area. Although ApproxADD provides a significant improvement in delay, power, and area, it may not be preferred for some of the error-resilient applications because its: (i) Error Distance (ED) is too high; and (ii) Error Rate (ER) increases rapidly with bit-width ( N ). To improve ED and ER, we exploit the concept of carry-lifetime and Error Detection and Correction logic, respectively. In this way, we introduce two more (improved) versions of ApproxADD--ApproxADD υ 1 and ApproxADD. We call these as ApproxADD υ 1 and ApproxADD υ 2 with existing approximate adders based on conventional design metrics and approximate computing design metrics. Furthermore, to inspect effectiveness of the proposed approach in real-life applications, we demonstrate image compression and decompression by replacing the conventional addition operations in Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) modules with ApproxADD υ 2.

Rapid evolution of E-world demands delay, power and area optimized digital circuits/systems while still meeting the security requirements of the cryptography applications. Cryptographic hash functions (which are considered the workhorse of security layers) provide compressive and non-invertible outputs. This signifies that approximate implementation of cryptographic hash functions can provide improvements in delay, power and area without considerable change in security level. In this paper, we first examine likelihood of infusing approximation in cryptographic hash functions and then propose a methodology to evaluate the effects of approximation. Further, we demonstrate four approximate pipelined implementations of Secure Hash Algorithm 1 (SHA-1). Our simulation results show that the proposed approximate pipelined SHA-1s provide significant improvements in delay, power and area with negligible change in security level.