Stochastic resonance is known as a phenomenon where the signal-to-noise ratio (SNR) of a nonlinear system improves by adding a proper level of noise. To facilitate this phenomenon, this paper proposes a stochastic-resonance analog-to-digital converter (SR ADC) based on a charge-redistribution capacitor digital-to-analog converter (CDAC). The proposed SR ADC utilizes the same architecture as a charge-redistribution successive approximation register (SAR) ADC. In this paper, the performance of the SR ADC is analyzed in detail to demonstrate its feasibility and advantage over the typical Nyquist ADC. The comparison with the SAR ADC in terms of the signal to noise and distortion ratio (SNDR) reveals that the SR ADC is useful to convert the weak input signal whose amplitude is comparable to the input-referred noise of the comparator.

Fractional-N phase-locked loops using Harmonic-Mixer (HM) based feedback offer good phase noise and spur performance without relying on complex calibration schemes. The HMs in prior art are often realized using the Sample-and-Hold (S/H) operation. This, however, can result in unwanted tones due to intermodulation, which must be suppressed using properly-designed filters. This paper proposes a simple and accurate analysis of the location and magnitude of these tones. We also provide a design guideline for the HM based on this analysis to properly suppress these tones. The results are supported through behavioral and transistor-level simulations.

We propose an all-standard-cell-based synthesizable successive-approximation-register analog-to-digital converter (SAR ADC) which is automatically placed and routed (P&R) using a commercial digital implementation tool. For higher feasibility and wider input range, a differential architecture is proposed with an inverter-based resistive digital-to-analog converter (RDAC) and a four-input comparator. MOSFET gate capacitance is employed for the sampling capacitor. To mitigate its capacitance variation due to input voltage and the leakage between gate and diffusion, we leave the diffusion of the standard cell floating and only use the capacitance between gate and bulk. Two prototypes have been designed in 65-nm bulk CMOS. Prototype I has been fabricated and achieves 10 MS/s, 14.3 mW, and 28.1-dB SNDR in a 6-bit architecture. The performance is improved in Prototype II by proposing a lookup table (LUT)-compensating transistor-configurable inverter-based RDAC and an OR-AND-Inverter (OAI)-based comparator and by employing a thick-oxide diffusion-floating decoupling cell for the sampling capacitor. The default LUT is created during the design phase by a script-controlled automatic simulation routine. The power consumption is significantly reduced as well through improved timing control. Layout-parasitic-extraction (LPE) simulations of Prototype II suggest 35.7- and 47.2-dB SNDRs in 6- and 8-bit versions, respectively. The power consumptions are reduced to 0.91 and 2.52 mW, respectively.

This paper presents a time-to-digital converter (TDC) using delta-sigma (ΔΣ) architecture which utilizes a charge pump as the time to voltage converter and a low bit SAR ADC as the quantizer. By never resetting the capacitor connected to the charge pump, a simple integrator is realized and first order noise shaping is achieved. This TDC is designed and simulated in 65 nm CMOS technology and can operate at 200 MHz sampling frequency. For 1 MHz bandwidth, simulation shows that this TDC achieves 74.9 dB SNDR and 269 fsrms integrated noise for ±1.5 ns input range. The proposed TDC consumes 0.9 mW power from 1 V power supply that translates to FoM of 99 fJ/conv.