In order to meet the increasing demand for more performance with reduced power consumption and chip form-factor, semiconductor manufacturing is moving toward 3-D stacked integrated circuits (SICs). One of the challenges in bringing this technology into realization is the complicated test accessibility requirements of 3-D chips, which apart from having adequate defect coverage, should also have minimal test time. A major limiting factor in test time improvement of ICs is the number of chip terminals, such as pins or through silicon vias (TSVs) available for bulk vector transport in testing. In the conventional design, a chip terminal is only used to either send or receive data at any given time. In this article, a test accessibility architecture based on ternary encoded simultaneous bidirectional signaling (SBS), intended for use in parallel test access mechanism (TAM) in system on chip (SoC)-based designs, is proposed. This method enables the use of chip terminals to simultaneously send and receive test vectors, effectively doubling the per-pin efficiency during testing. Experiments show that this technique reduces the overall test time (OTT) by up to 53.6% as compared to conventional TAM design methods.

Power electronics are widely used in the transport and energy sectors. Hence, the reliability of these power electronic components is critical to reducing the maintenance cost of these assets. It is vital that the health of these components is monitored for increasing the safety and availability of a system. The aim of this paper is to develop a prognostic technique for estimating the remaining useful life (RUL) of power electronic components. There is a need for an efficient prognostic algorithm that is embeddable and able to support on-board real-time decision-making. A time delay neural network (TDNN) is used in the development of failure modes for an insulated gate bipolar transistor (IGBT). Initially, the time delay neural network is constructed from training IGBTs' ageing samples. A stochastic process is performed for the estimation results to compute the probability of the health state during the degradation process. The proposed TDNN fusion with a statistical approach benefits the probability distribution function by improving the accuracy of the results of the TDDN in RUL prediction. The RUL (i.e., mean and confidence bounds) is then calculated from the simulation of the estimated degradation states. The prognostic results are evaluated using root mean square error (RMSE) and relative accuracy (RA) prognostic evaluation metrics.

Living organisms are complex systems, and yet they possess extremely high degrees of reliability. Since failures are local, their repair will often be taken on the local (cell) level. Engineers have long sought systems that could offer similar reliability and have relatively recently started trying to integrate ideas inspired by nature into the modern silicon technology of today. While bio-inspired proposals inspired by multicellular systems demonstrated feasibility, the resulting systems were often unduly complex. We are proposing a radically new methodology inspired by the characteristics, morphology, and behavior of simpler prokaryotic bacteria and bacterial communities. The hypothesis we use is that such simple unicellular organisms could help to build simpler cost effective systems, but with improved reliability than hitherto achieved by other methods. The result is a cellular array-based fault-tolerant electronic system with online self-test and self-repair capability. These ideas are simulated, tested, and verified through the successful construction of demonstrators: a proportional, integral, and differential and a robot controller. This paper discusses the underlying biological principles that guide our research and the bio-inspired model that we have derived. It also gives a detailed circuit and system description of the architecture and its run-time self-diagnostic and self-repair capability.

In this paper we have investigated the efficacy of applying multi-objective optimisation to Cartesian genetic programming (CGP) when used for evolution of cell-array configurations. A cell-array is a proposed type of custom FPGA, where digital circuits can be formed from interconnected configurable cells; thus, the CGP nodes are more complex than in its standard implementation. We have described modifications to a previously described optimisation algorithm that has led to significant improvements in performance; circuits close to a hand designed equivalent have been found, in terms of the optimised objectives. Additionally we have investigated the effect of circuit decomposition techniques on evolutionary performance. We found that using a hybrid of input and output decomposition techniques substantial reductions in evolution time were observed. Further, while the number of circuit inputs is the key factor for functional evolution time, the number of circuit outputs is the key factor for optimisation time.