The autoregressive nature of Large Language Models (LLMs) has enabled remarkable performance in language generation, making them a cornerstone in natural language processing. As context windows lengthen, the per-token key–value (KV) cache grows linearly with sequence length and turns the generation stage into a memory-bound operation. However, existing works focus primarily on an isolated stage of KV cache reduction, and most efforts incur significant hardware overheads. This results in a lack of cross-stage co-optimization and leaves significant reduction potential untapped. To address these challenges, we propose CrossKV, a software-hardware co-design architecture that accelerates LLM inference to fully achieve the potential of KV caching optimization. Motivated by our observation, we identify the three stages in KV caching and present a cross-stage co-optimization algorithm, including: a derivative-enhanced dynamic progressive pruning method, a DCT-driven key-vector low-rank compressing, and a dynamic clustered hybrid run-length encoding to reduce the KV caching while maintaining high accuracy. Then, an efficient architecture featuring cross-stage dynamic co-optimization with negligible hardware overhead is proposed to fully harness the algorithm of CrossKV. Our evaluations of CrossKV over 9 popular LLMs models and various long-context tasks demonstrate an average of$6.03\times $and$4.10\times $improvement for energy efficiency and speedup compared to existing SoTA Accelerators architecture. Compared to the Nvidia A100 GPU, CrossKV achieves an average$23.43\times $energy efficiency and$4.64\times $speedup, respectively.

Surface electromyography (sEMG) -based human-computer interaction (HCI) systems achieve high accuracy in controlled environments, but their robustness under daily life remains challenging. In real-world scenarios, variations in user posture introduce personalized biases that can significantly degrade model performance. A viable solution is to train a highly generalized network using existing data from various postures, enabling the model to become less sensitive to posture variations. In this work, we treat the original sEMG signals as a coupling of pattern and posture components, where each component can be considered as a causal signal specific to corresponding labels. We use the causal encoders to understand the generative relationships between data and labels, facilitating the disentanglement of components into different latent spaces and promoting clustering within each space. This enables the model to extract posture-invariant pattern components and train a robust pattern recognition model with strong generalization capabilities. We developed a high-density sEMG (HD-sEMG) dataset with 16 subjects performing in four common HCI postures, addressing the lack of posture variation samples in existing sEMG datasets. Our model achieved an average accuracy of 90.3% across four generalization tasks, outperforming other domain generalization models and demonstrating its superiority.

This paper presents a high-flexibility, high-CMRR instrumentation amplifier (IA) suitable for electrical impedance tomography (EIT) applications. It utilizes symmetric tunable pseudo-resistors to form a high-pass filter (HPF) at the amplifier’s front-end. The IA is highly flexible as it supports two distinct modes in tuning its bandpass corners. Due to the improved use of fully symmetrical drain networks and high output impedance source networks of the current-feedback instrumentation amplifier (CFIA)’s input stage, the IA circuit achieves a high common-mode rejection ratio (CMRR) of more than 90 dB at 1.5 MHz. The proposed IA has been simulated using a 180-nm CMOS process with a total input integrated noise within the 1 kHz – 2.356 MHz bandwidth below 20 μVrms. The entire circuit consumes 1.233 mW with a 3.3-V supply and occupies 0.146 mm2.

Frequency-domain features of peripheral physiological signals are vital for emotion recognition. However, existing end-to-end network architectures rarely extract them efficiently. To address this limitation, we propose a multimodal rU-Net model incorporating time-frequency information fusion. Specifically, the spectrum is integrated as a parallel branch alongside the time-domain branch for feature extraction. A fusion module enables direct frequency domain feature extraction and subsequent time-frequency fusion. By utilizing the rU-Net encoder with multimodal signal channels, our approach processes skin temperature (SKT), electrodermal activity (EDA), and photoplethysmography (PPG) data simultaneously, thus preventing model inflation from encoder stacking. The CASE and DEAP datasets have been validated using the leave-one-subject-out (LOSO) approach. In the 3-class classification, the best accuracy for valence (V) and arousal (A) were 69.36% and 71.34%, respectively, while in the 2-class classification V and A were 70.56% and 70.29%, respectively. This work offers valuable insights and a novel approach for future research in emotion recognition based on peripheral physiological signals collected by non-EEG wearable devices.

Electromyography (EMG) with individually unique characteristics, has emerged as a promising biometric trait. The capability to further encrypt EMG biometric patterns via distinct muscle activities (serve as a password), characterizes EMG biometrics with both a high recognition accuracy and revocability. The biometric component and the password component together form the global patterns of EMG. Previous EMG biometric verification methods directly extracted features from EMG signals to form global EMG representations with the biometric and password components entangled together. In this work, a disentanglement model was applied to disentangle the global EMG representations into password-specific and biometric-specific components in two separate latent spaces. The disentanglement model was built on a multibranch-encoder and single-decoder architecture. The two disentangled representations were learned separately by two cascaded support-vector domain description (SVDD) models. The model was trained and tested with data acquired on different days, to validate the interday robustness of our system, which is important for biometric verification using variable physiological signals. Results demonstrated that learning from disentangled representations contributes to a better EMG biometric verification performance compared with learning directly from the global representation. Our method achieved an Equal Error Rate (EER) of 0.0075 when impostors do not know the passwords. Furthermore, even when the impostors know the password, the biometric defense alone still managed to prevent intrusion with an EER of 0.1582. To the best of our knowledge, this is the first study to employ disentangled EMG representations for biometric verification.

This paper proposes a fully integrated charge pump (CP) with a double-loop control and a differentiator-based transient enhancer (DTE) for high-voltage neural stimulation applications. The double-loop control includes a clock-supply-voltage (VCLK) modulation loop and a pulse-frequency modulation (PFM) loop. The VCLKloop regulates the output voltage by adjusting VCLKwhile the PFM loop adjusts the operating frequency of the CP in accordance with the load current in order to improve power efficiency. The proposed CP combines the function of output voltage regulation and VCLKgeneration in a single unit, leading to significantly reduced circuit complexity. The proposed double-loop control is capable of dealing with different dc current requirements while the proposed DTE suppresses the possible undershoots and overshoots of the output voltage during load transients. The simulation shows that the proposed CP can provide a regulated 9-V output voltage from a 3.6-V input voltage with a peak power efficiency of 73.4% at 2-mA load condition. The overshoot and undershoot of the output voltage are kept below 3% when undergoing a 2-mA load transient.

Next-generation closed-loop epilepsy management system should be able to flag both the onset and termination of the ictal phase of repeated seizures, so that the neural stimulation profile can be tailor made to align to the optimal time frame for the best therapeutic outcomes. However, the presence of stimulation artifact (SA) makes it a significant challenge in implementing such a closed-loop system which requires concurrent recording of neural signals and stimulation of certain brain regions. High dynamic range (DR) is an important requirement for neural amplifiers to ensure lossless recording. We propose a high DR, rail-to-rail artifact tolerant system-on-a-chip (SoC). In the absence of SA, the SoC records and quantifies neural signals with low power consumption. When a stimulation artifact is detected, an additional ADC and a DAC are used to sample and reconstruct the artifact signal, respectively. The reconstructed artifact is then fed to the input of a differential amplifier as a common-mode signal for artifact removal. The target neural signal can subsequently be extracted by an independent component analysis algorithm. The technique has been verified using X-Fab’s 0.18-µm CMOS process. The simulation result suggests the power consumptions with and without artifact suppression are 15.6 and 46.5 µW, respectively. The input dynamic range of the SoC can be extended to 84.9-dB when an SA is detected.

This paper presents the design of a small-sized low-noise low-power analog front-end (AFE) amplifier for implantable multi-channel neural recording applications. The proposed amplifier consists of two stages, a chopper-stabilized capacitively-coupled instrumentation amplifier (CS-CCIA) followed by a programmable-gain amplifier (PGA). The amplifier can be set in either of the two modes: AP mode (300 ~ 10 kHz for capturing action potentials) and wide-band mode (1.5 ~ 10 kHz for capturing both local field potentials and action potentials). Depending on the neural signals of interest, the amplifier’s high-pass cut-off frequency for AP and wide-band modes is set by large pseudo resistors and a dedicated DC servo loop, respectively. In contrast to most existing designs in which the low-pass cut-off frequency is set by a dedicated filter circuit after the amplifier stages, the proposed amplifier sets a gain- independent low-pass cut-off frequency within the PGA, minimizing the size of the overall analog front-end. The proposed AFE has been fabricated using a 180-nm CMOS process, occupying a small area of 0.04 mm2. It consumes 3 μW under a 1.2-V supply. The input-referred noise is measured 4 µVrms in the action potential band and 4.6 µVrms in the wide band.

A neural stimulator with a 11.4 V voltage compliance under a 12 V supply voltage has been proposed. The stimulator ASIC has been realized using only low-voltage transistors in a$0.18-\mu\mathrm{m}$3.3 V triple-well CMOS process with deep N-well. The proposed stimulator continuously senses the voltage at the stimulating electrode and adaptively adjusts the bias voltages to the gate of stacked transistors in the output branch, ensuring the voltage stress on each individual transistor are all within the safety limit. The stimulator supplies biphasic stimulus current with a maximum stimulus current of$100\ \mu\mathrm{A}$and occupies 0.08 mm2area. The proposed low-voltage transistor implementation of a high-voltage stimulator is especially suitable for multi-channel closed-loop neuroprosthetic devices where the stimulator can be integrated with other units which typically operate from low voltage supplies, such as recording amplifiers and signal processing units.

Implantable neural stimulation is becoming increasingly popular for treating neurologically impaired patients. The charge balancing of the stimulus pulses is of paramount importance for the long-term safety of the electrode-tissue interface. This paper presents a novel neurostimulator ASIC in which two novel charge balancing schemes are proposed. One is based on acquiring the access resistance part of the inter-electrode impedance. The other scheme is based on acquiring the double-layer capacitance part of the inter-electrode impedance. This is in sharp contrast to the existing electrode impedance-aware charge balancing scheme which requires ADCs and computes the net charge in the digital domain. Hence the new impedance-aware charge-balancing scheme is more power friendly and can achieve charge balancing more quickly. The impedance-aware stimulator ASIC has been implemented using X-FAB's 180-nm CMOS process. The simulation results suggest that good charge balancing is achieved as the residual voltage on the electrode after the charge compensation reduces to 3.51 mV and 0.44 mV under the$R$s-based and$C_{\text{dl}}$-based charge balancing schemes., respectively.

There remains a need for satisfactory integrated sensors that can monitor humidity inside small active implanted devices in which delicate electronics are operating. This paper describes a simple capacitance-to-digits readout circuit for a capacitive humidity sensor for ultra-small medical implants. The proposed readout circuit provides a larger dynamic range than conventional capacitance readout circuits by removing the parasitic capacitance from the measured capacitive input. The circuit was designed in XFAB's 0.6-μm CMOS technology and provides 1 % resolution in measuring relative humidity.

This paper presents a high accuracy hand gesture recognition system based on electrical impedance tomography (EIT). The system interfaces the forearm using a wrist wrap with embedded electrodes. It measures the inner conductivity distributions caused by bone and muscle movement of the forearm in real-time and passes the data to a deep learning neural network for gesture recognition. The system has an EIT bandwidth of 500 kHz and a measured sensitivity in excess of 6.4 Ω per frame. Nineteen hand gestures are designed for recognition, and with the proposed round robin sub-grouping method, an accuracy of over 98% is achieved.

A high voltage supply is necessary for implantable stimulators that need to deliver high stimulus current to load tissue and overcome large electrode impedance. A constantly high supply voltage results in unnecessary power wastage in low-voltage stimulation and is potentially dangerous at the neural tissue interface. This paper presents the authors' recent progress in developing a stimulation system with self-adapting supply based on the previous Active Books system. The improved design is able to measure the peak electrode voltage on any specified anode and feed back the information to a central hub unit. If the peak electrode voltage is significantly lower than the current supply voltage, the adjustable voltage regulator in the hub will issue a lower but high enough supply voltage to power up the stimulator chip. The circuit has been designed and simulated in a 0.6-μm HV CMOS process.

We propose a novel dual-mode neural stimulator circuit. For stimulation requiring small or medium amount of charge, the stimulator supplies a constant current to the stimulation load in the same way as any standard current-mode stimulator. For high-charge stimulation applications, the stimulator supplies a variable stimulus current, depending on the voltage available across the current generator circuit. By adjusting the bias current accordingly, the stimulator maintains a high output impedance, independent of the stimulus current and the load voltage at the time. The total stimulus charge from the proposed stimulator is theoretically as high as voltage-mode stimulators. Simulated results using a 0.6-μm CMOS process are presented. At low stimulus current, the output impedance of the proposed stimulator circuit is at least six times higher than a conventional current-mode generator with constant bias current.

We present a current generator circuit which supplies two anodic currents for tripolar nerve stimulation. Depending on applications and the more convenient method of adjustment, the difference of the two anodic currents can be programmed using either of the two different modes. The reference current circuit in the current generator utilizes a gate-drain tied depletion transistor working in the triode region as the degenerating resistor in the Beta-multiplier topology. The negative temperature coefficient of the depletion transistor reduces the total sensitivity of the output current to temperature variation. The proposed current generator circuit is also stable over a wide range of supply voltages. Simulated results using a 0.6-μm CMOS process are presented. The temperature coefficient and power supply rejection ratio of the current generator are less than 0.06%/°C and 2%/V, respectively.

An integrated amplifier for electroneurogram (ENG) recordings from tripolar cuff electrodes is described. The amplifier is dedicated to urinary incontinence and other functional electrical stimulation (FES) applications. To remove myoelectric (EMG) interference a parallel RC network is used to balance the electrode impedances in the quasi-tripole amplifier configuration. The various ENG amplifier settings, such as resistance and capacitance trimming for the neutralization RC network, amplifier gain and filter cut-off frequencies, are controlled by an external microcontroller which communicates with the embedded SPI (Serial Port Interface) block in the amplifier. By this topology control of the ENG amplifier is executed in software allowing for the system parameters to be re-configured after implantation. The analog system blocks and details of the SPI logic are described. The amplifier was fabricated in a 3-V 0.35-mum BiCMOS process technology and preliminary measured results are reported. Input signals as low as 1muV can be reliably detected. The amplifier occupies an area of 1.5mm2and consumes about 1.4mW when configured to detect sub-microvolt neural signals.

There is a great demand to reduce the volume of implantable multi-channel stimulators for functional electrical stimulation applications. Miniaturization is currently limited by the size of the large off-chip blocking capacitors that are required for safety. This paper describes a fail-safe stimulator output stage circuit utilizing the principle of high-frequency current-switching, which allows the blocking capacitors to be integrated on-chip. The proposed circuit is based on the bridge rectifier circuit, hence fully utilizing the bidirectional current through the blocking capacitor. The approach has been verified by post-layout simulations in a 1 μm CMOS SOI technology.

The prime concern in the design of biomedical implants is safety. This paper addresses several safety features and proposes a new scheme to transmit power and data from the central implant to the stimulator "pods" while maintaining failsafe operation. The proposed scheme demultiplexes the stimulation command close to the electrodes and uses three wires in total to provide power and data to all stimulator "pods" from the central implant. Thus, it greatly reduces the number of wires routed to the stimulation sites and is able to stimulate more stimulator "peas". The circuit used to recover the power is shown, utilizing the three wires as the only inputs. The power recovery circuit features a varactor as the storage capacitor which gives a faster pumping speed than a linear capacitor. The idea is verified with circuit simulations in a 0.6μm CMOS technology. The proposed scheme ensures that in the event of cable failure, the current will be charge-balanced, thereby avoiding the generation of harmful electrochemical products.

The use of blocking capacitors in the output stages of implantable stimulators for functional electrical stimulation (FES) applications, is common practice for safety reasons. However, these capacitors tend to dominate the implant volume. This paper describes a stimulator output stage circuit which overcomes this limitation. The circuit features a novel capacitor reduction technique for implant miniaturization, and a simple failure-checking mechanism for enhanced reliability. The approach was verified by simulations in a 0.35 mum CMOS technology