Christian Berthet

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4ranked-venue papers

3as first author

0since 2021 · last 2002

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems 3 papers		Electronic design automation · 46% Integrated circuit design · 42% Embedded and real-time systems · 12%
Theoretical computer science 1 paper		Automated reasoning and model checking · 100%

Topics — the 8 heaviest of 9, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Integrated circuit design › system-on-chip system-on-chip design	1	2002	Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry · DAC 2002
Electronic design automation › hardware verification and test functional verification	1	1996	Functional Verification Methodology of Chameleon Processor · DAC 1996
Electronic design automation hardware verification and test	1	1996	Functional Verification Methodology of Chameleon Processor · DAC 1996
Embedded and real-time systems embedded system design	1	2002	Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry · DAC 2002
Electronic design automation › hardware verification and test hardware verification	1	1988	An Algebraic Model for Asynchronous Circuits Verification · IEEE Trans. Computers 1988
Electronic design automation › hardware verification and test › hardware verification › circuit-level verification switch-level verification	1	1988	An Algebraic Model for Asynchronous Circuits Verification · IEEE Trans. Computers 1988
Automated reasoning and model checking algebraic verification	1	1988	An Algebraic Model for Asynchronous Circuits Verification · IEEE Trans. Computers 1988
Integrated circuit design asynchronous circuit design	1	1988	An Algebraic Model for Asynchronous Circuits Verification · IEEE Trans. Computers 1988

Methods — techniques the papers use, named apart from their topics

functional verification · 0.0boolean algebra · 0.0characteristic functions · 0.0characteristic function · 0.0

Year	Publication	Venue	Position
2002	Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry abstract The complexity of a System-on-Chip design is not only in the million transistors packed in a square millimeter. The major challenge for technical success of a SoC is to make sure that millions lines of software fit in with millions gates. In this paper, the problematic of multi-million gate design is illustrated from the viewpoint of a practical development of a complex digital system done at STMicroelectronics for a GSM/GPRS cellular application. Christian Berthet	DAC	1
1996	Functional Verification Methodology of Chameleon Processor abstract Article Functional verification methodology of Chameleon processor Share on Authors: Françoise Casaubieilh Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Anthony McIsaac Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Mike Benjamin Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Mike Bartley Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , François Pogodalla Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Frédéric Rocheteau Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Mohamed Belhadj Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Jeremy Eggleton Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Gérard Mas Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Geoff Barrett Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Christian Berthet Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 421–426https://doi.org/10.1145/240518.240599Online:01 June 1996Publication History 23citation408DownloadsMetricsTotal Citations23Total Downloads408Last 12 Months5Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access Françoise Casaubieilh, Anthony McIsaac, Mike Benjamin, Mike Bartley, François Pogodalla, Frédéric Rocheteau, Mohamed Belhadj, Jeremy Eggleton, Gérard Mas, Geoff Barrett, Christian Berthet	DAC	11
1990	New ideas on symbolic manipulations of finite state machines abstract Formal verification of finite state machines (FSM) using symbolic manipulations is addressed. It is shown that the use of symbolic manipulations algorithms for the traversal of a FSM can be sublinear in the number of state and input patterns for some classes of machines. A symbolic manipulation algorithm can be directly used as a method for the transformation of a FSM which preserves the observable behavior. It is also shown that a backward traversal of a FSM can also be performed using symbolic techniques.> Christian Berthet, Olivier Coudert, Jean Christophe Madre	ICCD	1
1988	An Algebraic Model for Asynchronous Circuits Verification abstract An algebraic methodology for comparing switch-level circuits with higher-level specifications is presented. Switch-level networks, 'user' behavior, and input constraints are modeled as asynchronous machines. The model is based on the algebraic theory of characteristic functions (CF). An asynchronous automation is represented by a pair of CFs, called a dynamic CF (DCF): the first CF describes the potential stable states, and the second CF describes the possible transitions. The set of DCFs is a Boolean algebra. Machine composition and internal variables abstraction correspond, respectively, to the product and sum operations of the algebra. Internal variables can be abstracted under the presence of a domain constraint. The constraint is validated by comparison to the outside behavior. The model is well suited for speed-independent circuits for which the specification is given as a collection of properties. Verification reduces to the validation of Boolean inequalities.> Christian Berthet, Eduard Cerny	IEEE Trans. Computers	1