Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory architecture, and task mapping and scheduling. This paper presents an integer linear programming formulation for the task mapping and scheduling problem. The technique incorporates profiling-driven loop level task partitioning, task transformations, functional pipelining, and memory architecture aware data mapping to reduce system execution time. Experiments are conducted to evaluate the technique by implementing a series of DSP applications on several multi-core architectures based on dynamically reconfigurable processor cores. The results demonstrate that the proposed technique is able to generate high-quality mappings of realistic applications on the target multi-core architecture, achieving up to 1.3times parallel efficiency by employing only two dynamically reconfigurable processor cores.

Wireless Internet-access technologies have significant market potential, particularly the Worldwide Interoperability for Microwave Access (WiMAX) protocol which can offer data rates of tens of megabits per second. A significant demand for embedded high-performance WiMAX solutions is forcing designers to seek single-chip multicore systems that offer competitive advantages in terms of all performance metrics, such as speed, power, and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an application-specific integrated circuit, emerging dynamically reconfigurable (DR) processors are proving to be strong candidates for processing cores in future high-performance multicore-processor systems. This paper presents several new single-chip multicore architectures for the WiMAX application based on recently emerging coarse-grained DR processor cores. A simulation platform is proposed in order to explore and implement various multicore solutions combining different memory architectures and task-partitioning schemes. This paper describes the different architectures, the simulation environment, and several task-partitioning methods and demonstrates that up to 7.3 and 12 times speedup can be achieved by employing eight and ten DR processor cores for both the WiMAX transmitter and receiver sections, respectively. A comparison with other WiMAX multicore solutions is given in order to demonstrate that our best solution delivers a high throughput at relatively low area cost.

Wireless internet access technologies such as WiMAX have significant market potential. The high demand for embedded high performance WiMAX solutions is forcing designers to seek multi-core systems which offer competitive advantages in terms of all performance metrics. By providing the flexibility of a DSP with performance and power consumption approaching that of an ASIC, emerging dynamically reconfigurable processors are proving to be stronger candidates than conventional general-purpose processors or DSPs for future multi-core systems. This paper presents several multi-core solutions, based on newly emerging dynamically reconfigurable processor cores targeting WiMAX based applications. Coming with a SystemC trace-driven multi-core simulator, a simulation platform has been proposed in order to explore and implement various multi-core solutions combining different task partitioning strategies and inter-process communication methods.

This paper presents a new direct implementation of a popular RTOS with an associated application - the WiMAX physical layer - on reconfigurable computing architectures. A novel coarse-grained reconfigurable instruction cell based architecture is chosen as the target architecture. Firstly an RTOS - Micro C/OS-II - was ported to the target architecture, and then the WiMAX physical layer program was partitioned into multiple OS tasks which communicate with each other through the synchronization approaches provided by this RTOS. The WiMAX physical layer program has been also implemented on the ARM7TDMI processor. The results show that the performance of the target architecture is much better than the ARM7TDMI, and not limited by the bottleneck of memory latency.

This paper presents a solution based on parallel-pipelined architectures for high throughput and power efficient FFT IP cores. Low power consumption can be gained through the combination of hybrid low power algorithms and architectures. A number of IP cores have been implemented for the comparison of the impact of parameterization on power/area/speed performance. The results show that up to 55% and 52% power saving can be achieved by the combination of the above techniques for 64-point 4-parallel-pipelined FFT and 16-point 2-parallel-pipelined FFT respectively, as compared to R4SDC pipelined FFTs.

This paper proposes two novel parallel-pipelined FFT architectures, based on multiplier-less implementation, targeting wireless communication applications, such as IEEE 802.11 wireless baseband chip and MC-CDMA receiver. The proposed parallel-pipelined architectures have the advantages of high throughput and high power efficiency. The multiplier-less architecture uses shift and addition operations to realize complex multiplications. By combining a new commutator architecture, and a low power butterfly with this approach, the resulting power and area savings are up to 31% and 20% respectively, for 64-point and 16-point FFTs, as compared to parallel-pipelined FFTs based on Booth coded Wallace tree multipliers.