In this paper we present a macromodeling methodology to accurately reproduce the timing and the peak/average power behaviors of digital standard cells for a wide range of operating conditions determined by the load, the input transition time, and the supply variations. Our methodology significantly reduces the number of transient simulations for the cell characterization. The numerical results for the transient simulation of large digital systems indicate that we achieve a mean error of 10% for the power consumption and 4% for the propagation delay of the complete digital system while the mean error for the used gates in this system is 2.5% when compared to SPICE-based simulations.

In a synchronous clock distribution network with negligible skews, digital circuits switch simultaneously on the clock edge; therefore, they generate a lot of substrate noise due to the resulting sharp peaks on the supply current. A solution is to split a large design in different clock regions and introduce intentional clock skews between them, while taking the timing constraints into account. In this paper, the authors present a complete design flow to optimize the clock tree for less substrate-noise generation in large digital systems. It proposes a technique to assign combinatorial cells and flip-flops to the clock regions. It also takes into account the impact of unintentional clock skew such as jitter on the computed skews in order to assure a robust design. During the optimization, it uses compressed supply-current profiles to improve the CPU time. Experimental results show more than a factor-of-2 reduction in substrate-noise generation from large digital circuits of which the skews are optimized

Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate. It is therefore important to know the amount of noise at a certain point on the substrate. Existing transistor-level simulation approaches based on a substrate model extracted from layout information are not feasible for digital circuits of practical size. This paper presents a complete high-level methodology, which simulates a large digital standard cell-based design using a network of substrate macromodels, with one macromodel for each standard cell. Such macromodels can be constructed for both EPI-type and bulk-type substrates. Comparison of our substrate waveform analysis (SWAN) to several measurements and to several full SPICE simulations indicates that the substrate noise is simulated with our methodology within 10%-20% error in the time domain and within 2 dB relative error at the major resonance in the frequency domain. However, it is several orders of magnitude faster in CPU time than a full SPICE simulation.

The paper reports a novel simulation methodology for the analysis and prediction of substrate noise impact on analog/RF circuits taking into account the role of the parasitic resistance of the on-chip interconnect in the impact mechanism. This methodology allows investigation of the role of the separate devices (also parasitic devices) in the analog/RF circuit in the overall impact. In this way, it is revealed which devices have to be taken care of (shielding, topology change) to protect the circuit against substrate noise. The developed methodology is used to analyze the impact of substrate noise on a 3 GHz LC-tank voltage controlled oscillator (VCO) designed in a high-ohmic 0.18 /spl mu/m 1 PM6 CMOS technology. For this VCO (in the investigated frequency range from DC to 15 MHz) impact is mainly caused by resistive coupling of noise from the substrate to the non-ideal on-chip ground interconnect, resulting in analog ground bounce and frequency modulation. Hence, the presented test-case reveals the important role of the on-chip interconnect in the phenomenon of substrate noise impact.

Using wireless sensors placed on a person to continuously monitor health information is a promising new application. However, there are currently no models describing the radio channel around the human body making it difficult to design a suitable communication system. To address this problem, we have simulated electromagnetic wave propagation around the body and incorporated these results into a simple model. We then compared this model with measurements taken around the human torso and with previous studies in the literature. This paper proposes a simple statistical channel model useful for evaluating both UWB and (after resampling) narrow-band body area communication systems.

In a synchronous clock-distribution network, digital circuits switch simultaneously on the clock edge; therefore, they generate ground bounce due to sharp peaks of the supply current. We demonstrate an effective combination of two methodologies for ground-bounce reduction based on shaping the supply current: 1) introducing intentional skews to the synchronous clock network and 2) frequency modulation of the system clock. The former technique reduces the time-domain peaks as well as the spectral power of the supply current by spreading the simultaneous switching activities. The latter technique reduces the power contained in the clock harmonics by spreading this power into the side lobes formed around the clock harmonics without any change in the spectral power of the supply current. We also describe an analytical framework to analyze the impact of cycle-to-cycle variations of the supply current on the ground-bounce voltage. Simulation results for a 40K-gates circuit in a 0.18-/spl mu/m 1.8-V CMOS process on a bulk-type substrate show around 26 dB reduction in the spectral peaks of the ground-bounce spectrum at the circuit resonance and factors of 3.04/spl times/ and 2.64/spl times/ reduction in the peak-to-peak and RMS values, respectively, of the ground bounce in the time domain when these two techniques are combined. These two techniques are believed to be good candidates for the development of digital low-noise designs in CMOS technologies.

Nowadays, a lot of effort is spent on developing inexpensive orthogonal frequency-division multiplexing (OFDM) receivers. Especially, zero intermediate frequency (zero-IF) receivers are very appealing, because they avoid costly IF filters. However, zero-IF front-ends also introduce significant additional front-end distortion, such as IQ imbalance. Moreover, zero-IF does not solve the phase noise problem. Unfortunately, OFDM is very sensitive to the receiver nonidealities IQ imbalance and phase noise. Therefore, we developed a new estimation/compensation scheme to jointly combat the IQ imbalance and phase noise at baseband. In this letter, we describe the algorithms and present the performance results. Our compensation scheme eliminates the IQ imbalance based on one OFDM symbol and performs well in the presence of phase noise. The compensation scheme has a fast convergence and a small residual degradation: even for large IQ imbalance, the overall system performance for an OFDM-wireless local area network (WLAN) case study is within 0.6 dB of the optimal case. As such, our approach greatly relaxes the mismatch specifications and thus enables low-cost zero-IF receivers.

Substrate noise is a major obstacle for mixed-signal integration. In this paper we propose a fast and accurate high-level methodology to simulate substrate noise generated by large digital circuits. The methodology can handle any substrate type, e.g. bulk-type or EPI-type, and takes into account the effects of interconnect and supply. For each standard cell a substrate macromodel is used in order to efficiently simulate the total system, which consists of a network of such macromodels. For a 40K gates telecom circuit fabricated in a 0.18 mm CMOS process, measurements indicate that substrate noise is simulated by using our methodology within 20% error but several orders of magnitude faster in CPU time than a full SPICE simulation..

The digital switching noise that propagates through the chip substrate to the analogue circuitry on the same chip is a major limitation for mixed-signal SoC integration. In synchronous digital systems, digital circuits switch simultaneously on the clock edge, hereby generating a large ground bounce. In order to reduce the spectral peaks in the ground bounce spectrum, we combine the two techniques: (1) phase modulation of the clock; and (2) introducing intended clock skews to spread the switching activities. Experimental results show around 16 dB reductions in the spectral peaks of the noise spectrum when these two techniques are combined. These two techniques are believed to be good candidates for the development of methodologies for digital low-noise design techniques in future CMOS technologies.

The modeling of linear transfer functions is often required prior to the simulation of electronic systems. An example is the modeling of on-chip inductors starting from 2-port measurements. The modeling is often done using state-space models that can only represent proper systems. This leads to modeling problems in the case of improper systems such as in the case of 2-port modeling of the admittance matrix of an on-chip inductor. This paper first describes an extended state-space model to represent improper systems. Afterwards, the paper introduces an extension to classical frequency-domain subspace identification methods. The usefulness of both the extended state-space model and the extended subspace modeling technique are illustrated by comparing them with commercially available solutions. This includes a comparison on measurements of an on-chip inductor and on simulations of a coplanar waveguide.

Zero-IF transceivers are gaining interest because of their potential to enable low-cost OFDM terminals. However, the zero-IF architecture introduces IQ imbalance which may have a huge impact on the performance. Rather than increasing component cost to decrease the IQ imbalance, an alternative is to tolerate the IQ imbalance and compensate it digitally. Current solutions require extra analog hardware at the transmitter. We analyze transmit IQ imbalance estimation and propose a low-cost, highly effective estimation scheme, which is fully digital and located at the receiver. Performance analysis shows that this scheme can provide up to 4 dB gain while meeting the IEEE 802.11a constellation accuracy specification and more if larger IQ imbalance is present in the transmitter. It therefore enables the design of low-cost, low-complexity OFDM modems.

Fourth-generation wireless communication systems (4G) will have totally different requirements than what front-end designers have been coping with up to now. Designs must be targeted to multi-mode and reconfigurability, leading to the concept of a software-defined radio. A large part of such a radio will be integrated into a complex SoC, where the substrate noise coupling problem must be solved.However, for an optimal implementation of the complete system, including e.g. PA, RF filters and antenna, different technologies must be combined in a single package, merging the worlds of microwave 's-parameter' designers and IC 'spice' designers. Design and simulation environments efficiently combining the assets of both are needed.At the same time, optimized mixed-signal radio architectures including digital compensation techniques that overcome the limitations and inaccuracies of the analog front-end must be developed. Again, efficiently designing and simulating such mixed analog/digital architectures requires an optimized tool capable of combining RF simulation techniques with digital system model simulation.

Zero-IF receivers are gaining interest because they enable low-cost WLAN OFDM terminals. However, zero-IF receivers introduce IQ imbalance which may have a huge impact on performance. Rather than increasing component cost to decrease the IQ imbalance, an alternative is to tolerate the IQ imbalance and compensate it digitally. Current solutions converge too slowly for bursty WLAN communication. Moreover, the tremendous impact of a frequency offset on the IQ estimation/compensation problem is not considered. We analyze joint IQ-CFO estimation/compensation and propose a low-cost, highly effective compensation scheme. For large IQ imbalance (/spl epsi/=10%, /spl Delta//spl phi/=10/spl deg/) and large frequency offset, our solution results in an average remaining degradation below 0.5 dB compared to the reference case without IQ imbalance or frequency offset. It therefore enables the design of low-cost, low-complexity WLAN OFDM receivers.

Today a lot of attention is spent on developing inexpensive OFDM receivers. Especially, zero-IF receivers are very appealing, because they avoid costly IF filters. However, this implies IQ demodulation at RF, which therefore cannot be done digitally and thus introduces IQ mismatch. Unfortunately, OFDM is very sensitive to receiver IQ imbalance. Therefore, we developed a new compensation scheme to combat the IQ imbalance at baseband. In this paper, we describe the algorithm and represent the performance results. Our compensation scheme eliminates the IQ imbalance almost perfect. This leads to tremendous improvements, especially in multi-path channels (up to 10 dB performance gain), and enables low-cost zero-IF receivers.

There is an ongoing discussion in the broadband wireless world between OFDM and single-carrier. Single-carrier allows for more relaxed front-end requirements. OFDM, on the other hand, can yield better performance at low complexity. Recently, a new single-carrier scheme with frequency domain equalization and decision-feedback has been proposed for a SISO channel. This single-carrier scheme can reach the OFDM performance. We extend this new scheme for multiple antennas and multiple users. We show that this multi-user scheme with decision-feedback has a 3 dB gain over conventional linear single-carrier multi-user schemes and still maintains a low complexity. We illustrate that our scheme is equivalent with the generalized decision-feedback equalizer, but has a lower complexity.

The design of analog front-ends of digital telecommunication transceivers requires mixed-signal simulations at the architectural level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the architectural level, especially when the nonlinear behavior is frequency dependent. This paper describes an analysis and modeling method based on Volterra theory. The method derives bottom-up models of nonlinear analog continuous-time circuits. These behavioral models predict the dominant nonlinear effects using a composition of linear transfer functions and multiplications. This makes it possible to accurately model frequency dependencies and to gain insight into the dominant nonlinear sources of the circuit. The basic models are afterwards described using its multicarrier complex low-pass representation to enable their efficient cosimulation with the digital circuits in a dataflow simulation environment. The multicarrier representation is a direct extension of the classically used complex low-pass equivalent models, which considers the modulation of a single carrier only. The accuracy of the multicarrier representation is higher than classical complex low-pass equivalent models since out-of-band nonlinear distortion is taken into account. The main advantage of the proposed technique is that it yields both insight in the nonlinear behavior at the circuit level and that it provides an important gain in simulation efficiency of RF integrated circuits at the system level. Both aspects are demonstrated on a 5-GHz WLAN design.

Microelectromechanical systems (MEMS) components are gradually finding their way in communication applications. To fully understand their behavior in electrical circuits, an interpretable model is required that, in addition, can be simulated efficiently. This paper presents a model for a MEMS variable capacitor (varicap), that can be evaluated much more efficiently and equally accurate during circuit simulation than the differential equations that are normally used to describe this component. The model, based on Volterra series, describes the frequency dependence (e.g., the mechanical resonance) in combination with the nonlinear behavior of the MEMS varicap. The model is simple enough such that it can be interpreted by designers who want to use the MEMS varicap in RF communication circuits.

In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the clock edge, therefore they generate substrate noise due to the sharp peaks on the supply current. We present a novel methodology optimizing the clock tree for less substrate generation by using statistical single cycle supply current profiles computed for every clock region taking the timing constraints into account. Our methodology is novel as it uses an error-driven compressed data set during the optimization over a number of clock regions specified for a significant reduction in substrate noise. It also produces a quality analysis of the computed latencies as a function of the clock skew. The experimental results show >x2 reduction of substrate noise generation from the circuits having four clock regions of which the latencies are optimized.

RF front-end architectures of today's wireless applications need to meet tough requirements on nonlinear distortion to minimize unwanted effects such as crosstalk. An analysis of the nonlinear behavior of analog communication circuits or architectures is not straightforward. This paper presents a modified Volterra series approach to the simulation of nonlinear systems described at the architectural level. The total computed response is decomposed in its nonlinear contributions and the main nonlinearities can be identified. This yields a better insight into the system's nonlinear behavior and allows simplifications. The simplified system can then be simulated more efficiently. The implementation is only based on vector calculation to minimize the computation time, and has, been applied to a complete 5 GHz WLAN receiver front-end.

Designing complex analog systems needs different abstraction levels to reduce the overall complexity. The required level of abstraction depends on the accuracy and the purpose of the model. High-frequency amplifier mode-Is can vary from simple transfer functions for efficient bit-error-rate analysis up to detailed transistor level descriptions for accurate load-pull prediction. This paper introduces a nonlinear black-box model for high-frequency amplifiers. It extends the linear S-parameter representation to enable both efficient system-level simulations and load-pull prediction. Both are demonstrated on the measurements of a high-frequency amplifier excited using a WLAN-OFDM modulation.

Substrate noise generated by large digital circuits degrades the performance of analog circuits sharing the same substrate. Existing approaches usually extract the model of the substrate from the layout information and then simulate the extracted transistor-level netlist with this substrate model using a transistor-level simulator. For large digital circuits, the substrate simulation is however not feasible with a transistor-level simulator. In our previous work, it has been demonstrated that efficient and accurate simulation of substrate noise generation at gate-level is feasible. In this paper several important extensions to our previous work are introduced: modeling of I/O cells, modeling of input transition time and load dependency and the extraction methodology of an equivalent substrate model within multiple supply domains. Experimental results show an improved accuracy (6.3% error on RMS substrate voltage with respect to a full SPICE level simulation) with these extensions, while maintaining a large speedup with respect to SPICE simulations.

Multicarrier modulation schemes are widely used in several digital telecommunication systems, such as Asymmetric Digital Subscriber Lines (ADSL) and Wireless Local Area Network (WLAN) based on Orthogonal Frequency Domain Multiplexing (OFDM). An estimate of the Bit-Error-Rate (BER) degradation due to non-idealities in the transceiver (e.g. nonlinear distortions in the analog front-ends, digital clipping,...) is much more complicated in a multicarrier system than in a single-carrier system due to the large number of carriers and the huge number of possible transmitted symbols. This paper proposes a method for estimating the BER of such OFDM modulation schemes in a CPU time that is two orders of magnitude smaller than a Monte-Carlo method, as confirmed by simulations on a 5 GHz IEEE 802.11 WLAN receiver front-end.

In recent years, wireless indoor networks have received a lot of scientific and industrial attention. Most systems rely on the use of orthogonal frequency division multiplexing (OFDM) because of its capability to elegantly cope with multipath interference. However, while OFDM provides a nice solution for the digital modem, its front-end requirements should be investigated as well. To that goal, we have set up a simulation environment which comprises both the digital modem and the most important front-end nonidealities. We show that for the same data rate, bandwidth and transmit power constraints, Single-Carrier with Cyclic Prefix (SC-CP) allows the design of a more power-efficient modem than OFDM and is therefore a better candidate for portable wireless terminals.

Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total amount of generated substrate noise must be known. Simulating substrate noise generated by large digital circuits is however not feasible with existing circuit simulators and detailed substrate models due to the long simulation times and high memory requirements. We have developed a methodology to simulate this substrate noise generation at a higher level. Not only does this methodology take noise coupling from switching gates into account, but also noise coupling from the power supply is included. This paper describes this simulation methodology. In the paper it is shown that the high-level simulations correspond very well with SPICE simulations and that a large gain in simulation speed is obtained. This high-level simulation methodology makes it possible to predict substrate noise generation of large digital circuits in a very efficient way, early in the design flow of mixed-signal ASICs.

The explosion of the telecommunications market requires miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. New architectures must therefore be simulated at high level. Current methodologies and corresponding tools suffer from common drawbacks, such as lower accuracy, slow simulation speed, etc. A new methodology has been developped for the efficient simulation, at the architectural level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a multi-rate, multi-carrier signal representation together with a dataflow simulation scheme which switches dynamically towards the most efficient signal processing technique available. An implementation of this methodology shows both excellent runtimes and a high accuracy.

The design of analog front-ends of digital telecommunication transceivers requires simulations at the architectural level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the architectural level, especially when the nonlinear behavior is frequency dependent. This paper describes a method to derive a bottom-up model of nonlinear analog continuous-time circuits used in communication systems. The models take into account frequency dependence of the nonlinear behavior, making them suitable for wideband applications. Such model consists of a block diagram that corresponds to the most important contributions to the second- and third-order Volterra kernels of the output quantity (voltage or current) of a circuit. The examples in this paper, a high-level model of a CMOS low-noise amplifier and an active lowpass filter, demonstrate that the generated models can be efficiently evaluated in high-level dataflow-type simulations of mixed-signal front-ends and that they yield insight in the nonlinear behavior of the analog front-end blocks.

Future high-performance wireless communication applications such as wireless local area networks (WLANs) around 5 GHz require low-power and highly integrated transceiver solutions. The integration of the RF front end especially poses a great challenge in these applications, as traditional front-end implementations require a large number of external passive components. In this paper, we present the single-package integration of complete transceivers based on a thin-film multichip module (MCM) technology with integrated passives. The MCM substrate is a a common carrier onto which different ICs are mounted. passive components such as RF bandpass filters, inductors, capacitors, and resistors are directly integrated into the MCM substrate with the use of the multilayer structure of the MCM technology. The "system-on-a-package" approach is illustrated with a voltage-controlled oscillator for Digital European Cordless Telephone (DECT) applications and a 5-GHz WLAN front end. These examples indicate that this approach yields a compact low-power implementation of complete transceivers for high-performance wireless applications.

Although a single-chip solution seems to be ultimate goal for the design of wireless transceivers, there are many reasons to believe that this approach is not feasible for high performance applications. Especially the RF front-ends of these transceivers require components that are difficult to combine into one single chip. As an alternative we propose a single-package solution that contains different components that are interconnected with a multi-chip module (MCM) interconnect technology. By implementing passive front-end components directly into this interconnect technology, instead of using external commercial components, a cost-effective realization of the front-end can be obtained with a higher performance or a lower power consumption.

The complete application of a hierarchical top-down design methodology to analog sensor interface front-ends is presented: from system-level specifications down to implementation in silicon, including high-level synthesis, analog block generation and layout generation. A new approach for implementing accurate and fast estimators for the different blocks in the architecture is described. These estimators provide the essential link between the high-level synthesis and the block generation in our hierarchical top-down methodology. The methodology is illustrated by means of the design of a complex and realistic example. Measurement results are included.

This paper presents a high-level analysis and optimization tool for the design of analog RF receiver front-ends, which takes all design parameters and all aspects of performance degradation (noise, distortion, self-mixing...) into account. The simulations are performed in the spectral domain with a behavioral model library for the RF building blocks. The tool allows to explore alternative RF receiver topologies as well as to investigate design trade-offs within each topology. By having integrated the performance analysis routine within a simulated annealing optimization loop, the tool can also perform an optimal high-level synthesis of a given topology towards a specific application. It then determines the optimal specifications for the RF building blocks such that the required receiver signal quality is met while the overall power and/or area consumption is minimized.