Diagnosing chain failures is extremely important to ramp up production yield. Use of modern day low pin compressors limit the observability making chain diagnosis a difficult problem. When multiple chains fail during initial ramp up of yield, the high-resolution patterns are generally used for diagnosis. These patterns are generated using special ATPG settings and are very high in numbers. These high-resolution patterns burden the Automatic Test Equipment (ATE) with extra test time and test memory. In this work, we have developed a new algorithm to diagnose multiple chains using compressed production test pattern set. We believe that this is the first work which exhibits the use of production patterns to diagnose multiple chains. Diagnosing one chain at a time, this algorithm applies the information obtained so far to diagnose other chains. Experimental results show that up to 10 chains can be diagnosed simultaneously using compressed production patterns.

The Convolutional Neural Network (CNN) is a breakthrough technique in object classification and pattern recognition. It has enabled computers to achieve performance superior to humans in specialized image recognition tasks. Prior art CNNs learn object features by stacking multiple convolutional/non-linear layers in sequence on top of a classifier. In this work, we propose a Hierarchical CNN (HCNN) which is inspired by a coarse-to-fine human learning methodology. For a given dataset, we introduce a CNN-oriented clustering algorithm to separate classes into K subsets, which are referred to as families. Then, the HCNN algorithm trains K+1 classification CNNs: one CNN for family classification and K dedicated CNNs corresponding to each family for member classification. We evaluate this HCNN approach on the German Traffic Sign Recognition Benchmark (GTSRB), and achieve 99.67% correct detection rate (CDR), which is superior to the best reported results (99.46%) achieved by a single network.

We introduce an architecture for a programmable IEEE 802.11ah Wi-Fi modem based on a new Cadence Xtensa-based low-energy DSP. The design is based on a methodology for partitioning the system into hardware and software components that takes into account power consumption, silicon area and the need for programmability. Physical layer software functions avail the DSP's extensible architecture options for baseband processing, such as complex signal filtering and FFT acceleration instructions. We provide sensitivity data from software simulations and laboratory tests that demonstrate the modem is capable of reliable detection and decoding of 2MHz packets with -107dBm of received signal power. Additionally, we analyze latency requirements for a System-on-Chip (SoC) design.

Parallel file transfer protocol (PFTP) introduces the concept of data transfer using multiple parallel data paths between clusters. It makes use of striped data distributed across the multiple IO-nodes of a parallel file system on clusters. The protocol uses the striping format of the parallel file system to push multiple stripes of the file over multiple TCP connections. The flexibility in PFTP allows user to use different file transfer applications over these TCP connections. In this paper we describe the design architecture and implementation of PFTP. Several experiments explain how it improves the data transfer rate. We also provide performance results of PFTP for a varying file data size of 100 MB to 4GB. The flexible, secure, fault tolerant and high performance design of PFTP can be useful for large data grids.

Abstract This paper reports a study of sparse Matrix Vector Multiplication (MVM) on a parallel computing platform based on a fine‐grained multithreaded program execution model. Such sparse MVM computations, when parallelized without performing graph partitioning, suffers a very high communication to computation ratio, and is well known to have a very limited scalability on traditional distributed‐memory machines. The particular multithreaded system we use is the Efficient Architecture for Running THreads (EARTH) model, which can be implemented from off‐the‐shelf processors. With the Class B input sparse matrix from the NAS CG benchmark (75 000 rows), we attain an absolute speedup of 90 on 120 nodes of a distributed memory configuration. This is achieved without using inspector/executor or graph partitioning, or any communication minimization phase, which means that similar results can be expected for adaptive problems as well. High scalability is achieved because of a number of characteristics of the EARTH architecture: local synchronizations, low communication overheads, ability to overlap communication and computation, and low context‐switching costs. Copyright © 2002 John Wiley & Sons, Ltd.

We report on our work in developing a fine-grained multithreaded solution for the communication-intensive Conjugate Gradient (CG) problem. In our recent work, we developed a simple yet efficient program for sparse matrix-vector multiply on a multi-threaded system. This paper presents an effective mechanism for the reduction-broadcast phase, which is integrated with the sparse MVM, resulting in a scalable implementation of the complete CG application. Three major observations from our experiments on the EARTH multithreaded testbed are: (1) The scalability of our CG implementation is impressive, e.g., absolute speedup is 90 on 120 processors for the NAS CG class B input. (2) Our dataflow-style reduction-broadcast network based on fine-grain multithreading is twice as fast as a serial reduction scheme on the same system. (3) By slowing down the network by a factor of 2, no notable degradation of overall CG performance was observed.