Electroencephalography (EEG) plays a crucial role in the diagnosis of various neurological disorders. However, small hospitals and clinics often lack advanced EEG signal analysis systems and are prone to misinterpretation in manual EEG reading. This study proposes an innovative hybrid artificial intelligence (AI) system for automatic interpretation of EEG background activity and report generation. The system combines deep learning models for posterior dominant rhythm (PDR) prediction, unsupervised artifact removal, and expert-designed algorithms for abnormality detection. For PDR prediction, 1530 labeled EEGs were used, and the best ensemble model achieved a mean absolute error (MAE) of 0.237, a root mean square error (RMSE) of 0.359, an accuracy of 91.8% within a 0.6 Hz error, and an accuracy of 99% within a 1.2 Hz error. The AI system significantly outperformed neurologists in detecting generalized background slowing (p = 0.02; F1: AI 0.93, neurologists 0.82) and demonstrated improved focal abnormality detection, although not statistically significant (p = 0.79; F1: AI 0.71, neurologists 0.55). Validation on both an internal dataset and the Temple University Abnormal EEG Corpus showed consistent performance (F1: 0.884 and 0.835, respectively; p = 0.66), demonstrating generalizability. The use of large language models (LLMs) for report generation demonstrated 100% accuracy, verified by three other independent LLMs. This hybrid AI system provides an easily scalable and accurate solution for EEG interpretation in resource-limited settings, assisting neurologists in improving diagnostic accuracy and reducing misdiagnosis rates.

In this paper, the implementation to estimate the focus map spatially based on the intentional reblur of one image, which is the only input data, is presented. This enables flexible computation in the spatial domain, rather than the frequency domain. The gradient magnitude term widely used in image processing was used to derive a ratio map. The pixels closer to the focal point of the camera were on the thinner edge in the proposed ratio map. Oppositely, The edge was wider the when the pixels were far from the focal point. The core of proposed algorithm is introduced and the experimental results demonstrate the enhanced effectiveness, quality, and precision of the proposed algorithm.

The proposed system integrates the IEEE 1588 standard with the Pulse Per Second (PPS) mechanism to improve the accuracy of timing synchronization of the multiple nodes. A reference implementation for the virtual orchestra was given and introduced to evaluate the performance. It operates in the form of a character device driver and the application interface (API) was built for a programmer to use this proposed system. The experimental results show that the accuracy achieves the degree of several microseconds and the proposed system is acceptable for the application.

Scratchpad memory (SPM) has been increasingly used in embedded systems due to its higher efficiency in terms of energy and area compared to that of ordinary cache. A hybrid on-chip memory architecture that combines SPM with a mini-cache has been proposed. One key issue for hybrid on-chip memory architectures is to reduce the number of off-chip memory accesses and energy consumption. Existing methods achieve this by moving the most frequently accessed data into SPM. However, these methods may be ineffective because the main source of off-chip memory accesses may not be the most frequently accessed data. Instead, most off-chip memory accesses are caused by cache misses, so reducing the latter will reduce the former. Cache misses are mainly caused by data contending for cache lines. Therefore, this paper proposes a contention-aware SPM allocation method for hybrid on-chip management. The number of cache misses for a page is used as a metric to determine whether a page should be moved to SPM. When the number of misses for a page exceeds a threshold, the page is moved to SPM, reducing cache contention. Experimental results show that the proposed method can reduce the energy delay product by 35% to 53% compared to a cache-only on-chip memory architecture and 19% to 31% compared to an existing hybrid on-chip memory architecture.

Many consumer embedded system products nowadays are built on platforms with System-On-a-Chip (SOC) in which two or more processor cores, which are not necessarily of the same type, are put into a single chip and form the architecture of Chip-level Multi-Processor (CMP). Although such platform is capable of achieving high performance at relatively low cost, the system architecture of CMP brings new challenges in system development and increases complexity in developing embedded software especially at the level of kernel or operating system. This paper presents our experience and some preliminary results from building a multi-kernel embedded system with high performance Inter-Process Communication (IPC) mechanism for application software running on the platform of a newly developed multi-core SOC, namely PAC Duo SOC, which is the latest product from the PAC (short for Parallel Architecture Core) Project implemented at Industry Technology Research Institute (ITRI) in Taiwan. PAC Duo SOC is a heterogeneous multi-processor SOC composed of one ARM926 core serving as the general purpose processor (GPP) and two ITRI PAC DSP cores serving as the special purpose processors (SPP). We ported Linux operating system to run on the ARM926 processor and ported the real-time kernel Micro-C/OS-II to run on one PAC DSP core, leaving the other PAC DSP core with the option of running either another Micro-C/OS-II or a different kernel. To address the issues in IPC, a high performance message-passing mechanism is developed. Its design not only takes application-specific requirements into account but also takes advantages of hardware features.

In this letter, a novel image restoring technique for interlaced video is presented. We employ a motion-degree detector to determine the type of motion in the adjacent pictures efficiently and a hybrid interpolation based on spatial and/or temporal information to restore the missing pixels for each motion type. Extensive experimental results demonstrate that our method can obtain better performances in terms of both quantitative evaluation and visual quality than the state-of-the-art image restoring techniques. Since the proposed method requires low computational complexity, it is very suitable for real-time hardware implementation and can be applied to current television systems.