Advanced Metering Infrastructure (AMI) systems constitute a vital part for the interconnection of the electrical grid towards enabling the smart grid area. They enable real-time electrical measurement exchange through a utility platform, in order to activate billing and load demand forecasting processes. However, the cyber-attack surface of such systems has increased over the latest years. The attacks are becoming highly sophisticated and cannot be detected by the existing cyber-security mechanisms. To cope with this challenge, these mechanisms should start incorporating knowledge about adversarial Tactics, Techniques are Procedures (TTPs). To achieve this, deception tools are used to lure adversaries by introducing an environment that resembles the actual system. In this paper we propose AMINet, which builds on a composition of well-known deception tools as honeypots to form a honeynet for AMI systems. Specifically, this work focuses on AMINet first architectural design with an emphasis on its emulation capabilities on the behavior and interactions between smart meters and the utility platform using the DLMS/COSEM protocol. Furthermore, AMINet is deployed in an production-level AMI infrastructure and compared against the actual AMI system that is available on the utility business side. The comparison results demonstrate a similar behavior, which is validated through initial tests on functional and non-functional requirements. Additionally, the existing small set of static attacks running in the infrastructure is enriched by more sophisticated attacks and AMINet aids towards the development of dedicated detection tools by logging the adversarial interactions.

Lattice based cryptography can be considered a candidate alternative for post-quantum cryptosystems offering key exchange, digital signature and encryption functionality. Number Theoretic Transform (NTT) can be utilized to achieve better performance for these functionalities, where polynomials are needed to be multiplied. NTT simplifies the multiplication overhead allowing point-wise multiplication by transforming the polynomials into the spectral domain and then inversing the result to the original domain. It is important to optimize this technique that is used in a wide range of computing systems. In this paper we study the feasibility of using OpenCL, a portable framework, to implement a parallelized version of NTT which allows deployment on heterogeneous platforms, such as Graphic Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). We measure the performance of our implementation on a GPU and evaluate when and where such a deployment is beneficial. Our results showed that the proposed parallel implementation is a viable acceleration approach for these algorithms for lattice-based cryptography solutions.

In this work, the implementations of the LBlock, Piccolo, Twine, and Klein lightweight ciphers in FPGA technology are studied in terms of area, frequency, throughput, and throughput/area. To accomplish this, loop unrolling and pipelining were employed in two phases. In the first phase, different loop unrolling factors were used to implement the round function of each cipher, while in the second phase, 2-stage pipelining with loop unrolling per stage was applied. The produced designs were implemented in Xilinx (Kintex-7) FPGA technology. Based on the implementation results, a detailed study on the above-mentioned design metrics was performed and important outcomes were derived.

IoT is a rapidly expanding environment. More and more devices, from the most high-end smartphones, to the most modest environmental sensors, already exhibit or acquire the ability to communicate with each other and be parts of networks. Connectivity is mainly accomplished through wireless communications and privacy is the way to go, regarding security over the air. A common approach dictates the incorporation of a crypto-core inside the transceiver. However, a privacy implementation must take into account several restrictions, imposed by the constrained resources of a small, power efficient device. For this purpose, an incorporation of a hardware implemented lightweight Simeck32/64 block cipher for IEEE 802.15.4 transceiver was proposed. In this work, we examine the FPGA implementation cost of such an approach, and we propose newly designed and efficient implementations of the proposed Simeck32/64 Crypto-Core. Our implementations achieve great improvement in throughput values, with a reasonable increase in hardware area. Furthermore, modifications of these approaches, exploiting the special functional blocks of a Xilinx FPGA, namely BRAM and DSP blocks, are implemented and the achieved results are evaluated. Additionally, the effects of applying the DSP multi-pumping methodology on the aforementioned implementations are also examined.

Binary Edwards Curves (BEC) constitute an alternative to the standardized Weierstrass elliptic curve (EC) equations since the latter have intrinsic side channel attack vulnerabilities due to their lack of point operation uniformity. Thus, BECs have gained popularity over the past few years due to their uniformity, operation regularity, completeness and implementation attractiveness. However, BEC Scalar multiplication hardware implementations are still lacking in performance when compared to their Weierstrass equivalent. In this paper, a design strategy/methodology is proposed in order to realizeBEC Scalar multipliers with a good trade-off between computation speed and utilized hardware resources. The strategy is based on a GF(2k) operations parallelism mechanism that aims at the minimization of idle states in the utilized processing elements as well as the minimization of employed storage andcontrol elements. A BEC SM architecture is proposed in order to describe the realization of the proposed strategy and its benefits are analyzed. In order to evaluate the efficiency of the proposed architecture an implementation was made in FPGA technology for GF(2^233) fields with BECs using d1 = d2. Whencompared to other works, the implementation expressed very balanced results.

Taking into account the high regularity and completeness of Binary Edwards Curves (BEC), BEC point operation efficient implementation in hardware becomes a need especially since such curves tend to be more resistant against side channel attacks than the classical Weierstrass Elliptic Curves. However, BECs require more GF(2k) operations for a single scalar multiplication. This constitutes a deterring factor for their wide adoption and standardization. In this paper, a design methodology, hardware architecture and implementation is proposed on the efficient implementation of BEC scalar multiplication accelerators. To achieve that, a parallelism approach is introduced on affine coordinate representation BECs supporting fast GF(2k) inversion through a GF(2k) inversion algorithm capable of realizing also GF(2k) multiplication. The resulting architecture using 4 parallel operating GF(2k) arithmetic units when implemented in FPGA technology provide better results than similar Weierstrass Curves following parallelism techniques, indicated that BECs support parallelism better than their Weierstrass equivalent.

In this paper, a methodology towards a hardware/software implementation of an Elliptic Curve Diffie Hellman (ECDH) scheme is proposed in an effort to overcome the design problems of Elliptic Curve Cryptography (ECC) systems stemming from the highly constrained embedded system hardware and software environment (restricted RAM, storage and processing power). To achieve that, instead of the excessively slow software ECDH implementations or monolithic, not flexible hardware implementations, we propose the use of a flexible, scalar multiplication (SM) accelerator connected to the main embedded system processor in order to speed up ECDH functionality without downgrading the overall main processor performance. The proposed solution can be used for a wide variety of GF(2k) based Elliptic Curves (EC) and is capable of shifting from one EC to another EC at runtime (flexibility). The proposed architecture was implemented and tested in Xilinx Virtex 5 technology by realizing the proposed SM accelerator unit interconnected with a Xilinx microblaze softcore processor.

Point Multiplication (PM) is considered the most computationally complex and resource hungry Elliptic Curve Cryptography (ECC) related mathematic operation. The design of PM hardware accelerators follows approaches that have a trade off between utilized hardware resources and computation speed. In this paper, the above trade-off and its relation with the operations of the GF(2k) defining the Elliptic Curve (EC) is highlighted and investigated. Following this direction, a point operation design methodology based on the parallelization and scheduling of GF(2k) operations is proposed. This design approach is adapted to the PM employed GF(2k) multiplication algorithm and associated implementation in an effort to increase PM accelerator speed with an acceptable cost on chip covered area (hardware resources). Using the proposed methodology, two PM accelerator hardware architectures were proposed based on bit serial and bit parallel GF(2k) multipliers that, when implemented in FPGA technology, proved to be very fast in comparison to other similar works.

RSA cryptographic algorithm has long achieved cryptographic and market maturity. However, RSA implementations, after the discovery of Side Channel Attacks (SCA), are susceptible to a variety of different attacks that target the hardware structure rather than the algorithm itself. There are a wide range of countermeasures that can be applied on the RSA structure in order to protect the algorithm from SCAs, however few of them are efficient in hardware since they add extensive performance cost to an SCA resistant RSA implementation. In this paper, a hardware architecture is proposed based on a Fault attack (FA) and Simple Power attack (SPA) resistant algorithm for Chinese Remainder Theorem (CRT) RSA that through the principles of parallelism and component reusability can guarantee hardware efficiency. We describe an implementation approach based on Montgomery modular multiplication and also propose a testing hardware architecture to simulate the security chip environment that our FA-SPA resistant CRT RSA can be integrated in. The designed architecture is implemented in FPGA technology and results on its time and space complexity are extracted and evaluated.

RSA cryptographic algorithm, working as a security tool for many years, has long achieved cryptographic and market maturity. However, as all crypto algorithms, RSA implementations, after the discovery and wide spread of Side Channel Attacks (SCA), are susceptible to a wide variety of different attacks that target the hardware structure rather than the algorithm itself. While there are a wide range of countermeasures that can be applied on the RSA structure in order to protect the algorithm from SCAs, combining several such measures in order to guarantee an SCA resistant RSA design is not an easy job. There are many incompatibility issues among SCA protection methods as well as an extensive performance cost added to an SCA secure RSA implementation. In this paper, we address some very popular and potent SCAs against RSA like Fault attacks (FA), Simple Power attacks (SPA), Doubling attacks (DA) and Differential Power attacks (DPA), and propose an algorithmic modification of RSA based on Chinese Remainder Theorem (CRT) that can thwart those attacks. We describe an implementation approach based on Montgomery modular multiplication and propose a hardware architecture for a SCA resistant CRT RSA that is structured on our proposed algorithm. The designed architecture is implemented in FPGA technology and results on its time and space complexity are extracted and evaluated.

IETF's new Forwarding and Control Element Separation (ForCES) architecture specifies the ForCES model providing an accurate description of the Forwarding Plane in an Object-Oriented fashion. However, the model is described totally in an XML Schema Definition (XSD): it is well-defined but purely machine oriented, being readable and usable, thus not human-friendly and difficult extending itself in the future. We argue that the ForCES model is actually a meta-model that is used to model ForCES components, e.g. Logical Function Blocks (LFBs), that later are used in ForCES applications. This paper presents a methodology based on a case study on how to automate the process of configuring the forwarding plane of network devices using state-of-the-art model-driven techniques in a tangible way while specifying a tool supported by a Domain Specific Language (DSL) for ForCES. We first consider describing the ForCES XSD based meta-model to a more manageable Ecore (MOF) based meta-model and then we create a DSL based on this Ecore meta-model. Then we target to transform automatically a Platform Independent ForCES model specified in the DSL to an executable target source code (Platform Specific: XML-ForCES compliant, C++, Java) able to communicate with the ForCES protocol.

The need for small chip covered area in most handheld devices with out sacrifices in computational power introduces an interesting problem concerning expensive, computational intensive operations, like GF(2k) inversion which is widely used in cryptography. This paper addresses this problem by proposing a systolic inversion architecture for GF(2k) fields. This architecture is based on an extended analysis on an optimized version of modified extended Euclidean algorithm (OMEEA) that is using signal reusability and simplification of the control signals with regard to hardware design and manages to make the inversion process less complex. The proposed one dimensional systolic inversion architecture based on OMEEA was measured in terms of hardware components number, latency and critical path delay with very interesting results when compared to other well known designs thus proving the efficiency of the analysis on OMEEA algorithm.

In this paper, a generic elliptic curve (EC) arithmetic unit with high flexibility and small chip covered area is proposed. This EC arithmetic unit is based on the one dimensional systolic architectural realization of a proposed modified multiplication - inversion algorithm that through appropriate initialization uses the algorithmic structure of inversion to also perform multiplication. The proposed architecture is realized on FPGA for GF(2163) and is compared with similar up-to-date designs. The proposed EC arithmetic unit has very small chip covered area without any serious penalty in calculation delay and since is designed on the affine coordinate plane, it offers a good side channel attack resistance base for further optimizations on this field.

An architecture and VLSI implementation of a new block cipher called Curupira is presented in this paper. This cipher is suitable for wireless sensors and RFID applications. Our 0.13 mum implementation requires resources of 9450 gate equivalences and is capable to encrypt a plaintext in 10 clock cycles. The cipher achieves a maximum throughput up to 2361 Mbps at 246 MHz for encrypting/decrypting. When clocked at 100 KHz a throughput of up to 960 Kbps is achieved and an average power of 0.04 mW is drawn.

Elliptic curve cryptography (ECC) is a very promising cryptographic method, offering the same security level as traditional public key cryptosystems (RSA, El Gamal) but with considerably smaller key lengths. To increase the performance of an EC Cryptosystem, dedicated hardware is employed for all EC point operations. However, the computational complexity and hardware resources of an Elliptic Curve processing unit are very high and depend on the efficient design of the Elliptic Curvepsilas underlined GF(2k) Field. In this paper, we propose an EC arithmetic unit that is structured over a high peformance, low gate number GF(2k) arithmetic unit. This proposed GF(2k) arithmetic unit is based on one dimensional systolic architecture that can perform GF(2k) multiplication and inversion with only the performance cost of inversion. This is achieved by utilizing a multiplication/inversion algorithm based on the modified extended Euclidean algorithm.

This paper presents P2P-InfoReflect, a system for supporting multi-attribute range queries. Our system differs from the already proposed in two major areas. The first is the decoupling of the routing process from the object distribution process due to the novel architecture that we propose. In this way we can separately optimize our system in order to efficiently implement these two functionalities. The second is the distributed creation and optimization of a locality aware overlay where routing process is performed in a balanced manner. The two algorithms that we proposed towards this goal, the placement and the swapping algorithm, are presented and analyzed in detail. Our claims are supported through our evaluation that shows the negligible overhead that our architecture introduces its scalable behavior and the improvement in the performance of our system with the development of a locality aware overlay.

Abstract Universal mobile telecommunication system (UMTS) has specified security mechanisms with extra features compared to the security mechanisms of previous mobile communication systems (GSM, DECT). A hardware implementation of the UMTS security mechanism is presented in this paper. The proposed VLSI system supports the Authentication and Key Agreement procedure (AKA), the data confidentiality procedure, and the integrity protection procedure. The AKA procedure is based on RIJNDAEL Block Cipher. An efficient RIJNDAEL architecture is proposed in order to minimize the usage of hardware resources. The proposed implementation performs the AKA procedure within 76 µs comparing with the 500 ms that UMTS specifies. The data confidentiality and the integrity protection is based on KASUMI Block Cipher. The proposed KASUMI architecture reduces the hardware resources and power consumption. It uses feedback logic and positive‐negative edge‐triggered pipeline in order to make the critical path shorter, without increasing the execution latency. The S‐BOXes that are used from RIJNDAEL and KASUMI block ciphers have been implemented with combinational logic as well as with ROM blocks. Copyright © 2006 John Wiley & Sons, Ltd.

Existing solutions to create topology aware DHTs result in a highly unbalanced system in terms of routing load and space distribution. Accordingly, network applications and services that require DHT systems to reflect locality without compromising load balance currently fail from exploiting the advantages, e.g. scalability, claimed by peer-to-peer systems. In this paper, we propose a novel and general DHT architecture which combines the desirable properties of a well balanced DHT with those of an overlay which can dynamically reflect the underlying network topology. As a result, our system can be efficiently used by a wide range of network applications and services.

Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decryption process. They reduce the required hardware resources and achieve high-speed performance. Their design philosophy is completely different. The first uses feedback logic and reaches a throughput value equal to 259 Mbit/sec. It performs efficiently in applications with low covered area resources. The second architecture is optimized for high-speed performance using pipelined technique. Its throughput can reach 3.65 Gbit/sec.

In this paper an accurate, analytical model for the evaluation of the CMOS inverter delay in the sub-micron regime, is presented. A detailed analysis of the inverter operation is provided which results in accurate expressions describing the output waveform. These analytical expressions are valid for all the inverter operation regions and input waveform slopes. They take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The presented model shows clearly the influence of the inverter design characteristics, the load capacitance, and the slope of the input waveform driving the inverter on the propagation delay. The results are in excellent agreement with SPICE simulations.

This paper presents an accurate model for the evaluation of the CMOS short-circuit power dissipation for short-channel devices, on the basis of a CMOS inverter. The improvement of the proposed approach against previous works is due to the new derived, accurate, analytical expressions for the inverter output waveform which include for the first time the influences of both transistor currents, and the gate-to-drain coupling capacitance. The results produced by she suggested model show good agreement with SPICE simulations.

A novel space-time representation of iterative algorithms, which can be expressed in nested loop form and may include non-constant dependencies is proposed and a systematic methodology for their mapping onto regular processor arrays is presented. In contrast to previous design methodologies, the execution time of any variable instance is explicitly expressed in the Dependence Graph, by the construction of the Space-Time Dependence Graph (STDG). This approach avoids the uniformization step of the algorithm and the requirement for fully indexing the variables.

An analysis of potential parallelism in TCP/IP is presented for two purposes. First, it is used as a basis for an implementation on a multiprocessing platform. Second, it reveals the areas where protocol modifications and/or tuning would yield more efficient implementations on multiprocessors. The focus is on the analysis, and detailed dependence graphs among the atomic TCP/IP protocol functions are presented. No specific implementation design is shown, since this highly depends on the particular hardware chosen.>